Sr SOC Emulation Validation Engineer

Intel Corporation; Kulim; Hybrid; MYR 120,000 - 240,000; Full time

Job summary

Intel Corporation is seeking an experienced Emulation Engineer to validate next-generation Intel Client SoC Fullchip. You will define validation strategy, develop emulation models from RTL, and create tools to accelerate pre-silicon validation while collaborating with design teams and architects.

The role involves close work with IU/SoC validation teams to optimize environments, test suites, and automation, and requires a BS/MS in a relevant field with 8+ years of emulation experience.

Qualifications

• BS /MS in Electronics/Electrical or Computer Engineering or Computer Science with at least 8 years of experience in emulation.

Responsibilities

• Create emulation models from an RTL design and document RTL changes.
• Develop hardware/software collateral and integrate with the emulation model.
• Test and debug the emulation model and collateral.
• Define and develop new HW/SW tools to accelerate RTL and improve emulation usability.

Skills

RTL emulation

Validation strategy

Automation

Education

BS/MS in Electronics/EE or CE or CS

Job description

## Job Description:Come join us to work on Intel's next generation Client CPU SoC with latest process technology in the era of hyper scale computing. This position involves validation of the next generation of Intel Client SoC Full chip, with a unique opportunity to work on next generation process nodes . Responsible to define next generation validation strategy ensuring they meet product specification and functionality before they are productized into physical chip, drive innovation and changes required in validation to incorporate ML/AI based strategic initiatives to improve quality and efficiency. Successful applicants will be required to work very closely with design teams and architects to implement the low-level Register Transfer Logic (RTL) design to ensure overall good functionality of the chip. Develop specific test environment/platform, validation strategy, methodology and test plan to validate System on Chip SOC design by identifying and exercising boundary conditions and special cases in an effort to break the chip to find that last elusive bug. As an SOC Fullchip and Emulation Engineer, you will be responsible but not limited to: * Creating emulation models from a Register Transfer Level (RTL) design.* Defining and documents RTL changes required for emulation model.* Developing hardware and software collaterals and integrates it with the emulation model.* Testing and debugging the emulation model and collateral.* Defining and developing new capabilities and HW/SW tools to enable acceleration of RTL and improve emulation model usability for pre-silicon functional validation.* Developing improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform.* Interfacing with and provides guidance to IU/SoC validation teams for optimizing their validation environments, test suites and methodologies for emulation efficiency.* Developing and applying automation aids, flows and scripts in support of emulation ease to use and improvement of equipment utilization.## **Qualifications:**This position requires a BS /MS in Electronics/Electrical or Computer Engineering or Computer Science with at least 8 years of experience in emulation.## Job Type:Experienced Hire## Shift:Shift 1 (Malaysia)## Primary Location:Malaysia, Penang## Additional Locations:Malaysia, Kulim## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \\* Job posting details (such as work model, location or time type) are subject to change.