Sr. Analog Layout Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance.

THE ROLE:

AMD is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry leading CAD tools and cutting-edge foundry technology. Examples of layout designed by our team include Phase Locked Loop (PLL), Delay Locked Loop (DLL), Voltage Controlled Oscillator (VCO), Digital to Analog Converter (DAC), Current Regulator, High Speed Differential Signalling circuitry, Droop Detect, and Die Crack Monitor. Proficiency in 2D layout design while being able to visualize in 3D space are traits ideal for this position. It is useful to have knowledge of digital and analog circuitry at the CMOS transistor level.

THE PERSON:

An experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious.

KEY RESPONSIBILITIES:

• Layout of basic digital and analog building blocks using analog transistor level components.
• Layout of analog macros, power pads, and input/output pads using above blocks.
• Working closely with Analog designers in floorplanning; power grid and signal flow planning.
• Physical and electrical verification including DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD.
• Creation of blackbox models for other groups in the design flow.

PREFERRED EXPERIENCE:

• Must have detailed knowledge of CMOS circuit theory.
• Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout.
• Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools.
• Knowledge of chip level integration and ESD concepts is a plus.
• Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability.
• Good understanding of signal and clock shielding and isolation techniques.
• Ability to work well as part of a team.

ACADEMIC CREDENTIALS:

• Bachelor’s degree in Engineering (or related field) OR Associates Degree in Engineering.

LOCATION:

Penang, Malaysia

Benefits offered are described: AMD benefits at a glance.