Silicon Integration Design Engineer - Timing Model

Lattice Semiconductor; Penang; On-site; MYR 90,000 - 130,000; Full time

Job summary

Lattice Semiconductor in Penang, Malaysia, is seeking an experienced FPGA timing model engineer to join our hardware integration team. You will collaborate with IP designers to align timing models with FPGA tool specifications and deliver robust timing references based on SPICE/STA data.

The ideal candidate has 10+ years in hardware integration, strong Cadence Virtuoso experience, and proficiency in SystemVerilog, synthesis, and timing analysis, with scripting skills in Linux and Python to

Qualifications

• 10+ years of hardware integration design and FPGA timing model know-how.
• Expertise in timing model development and verification against IP requirements.
• Proficient in Cadence Virtuoso schematic generation and SPICE simulations.
• Strong knowledge of SystemVerilog, synthesis, and static timing analysis.
• Experience with floor-planning and power estimation in back-end flows.

Responsibilities

• Collaborate with IP designers to ensure timing models meet FPGA tool specs.
• Define timing arcs and constraints per IP specifications for software teams.
• Perform quality checks on timing models and fix missing arcs or clocks.
• Generate full-chip timing models bridging IP models and STA reports.
• Apply Linux scripting and Python to automate timing data analysis.

Skills

Timing model development

Cadence Virtuoso

SystemVerilog

Synthesis

Static timing analysis

Floorplanning

Power estimation

Linux scripting

Python

Tools

Cadence Virtuoso

SPICE

PrimeTime

Liberate

Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description: Detailed Description

• Collaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.
• Understand IP functionality to define timing arcs and constraints per spec and deliver to software team.
• Perform quality checks on timing models to confirm all timing arcs meet software requirements.
• Address issues such as missing timing arcs and missing clock information.
• Generate timing reference models based on IP requirements.
• Compare timing models: Current proprietary format vs. Liberty format (.lib).
• Handle custom design simulations, use SPICE simulations and additional data to construct proprietary Timing models.
• Generate full chip timing model to bridge between IP timing models, using SPICE simulations or STA reports.
• FPGA power model know-how and knowledge will be added advantage.
• Experience with PrimeTime/Liberate will be added advantage.
• Additional Job Description 10 yrs experience of hardware integration design FPGA timing model know-how and knowledge will be added advantage.
• Successfully went through whole development from start to Tape Out of at least 2 products.
• Proficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.
• Working knowledge of System Verilog, synthesis, and static timing analysis.
• Specialist in floor-planning, power estimate, timing and back-end methodologies.
• Experience with Linux scripting and Python.
• Experience and knowledge of PnR is a plus.
• Strong written and oral communication skills.
• The ability to stay up-to-date with the latest advancements in technology & design.
• Ability to leverage AI tools to accelerate content creation, use AI to analyze large datasets and identify patterns.

• Collaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.
• Understand IP functionality to define timing arcs and constraints per spec and deliver to software team.
• Perform quality checks on timing models to confirm all timing arcs meet software requirements.
• Address issues such as missing timing arcs and missing clock information.
• Generate timing reference models based on IP requirements.
• Compare timing models: Current proprietary format vs. Liberty format (.lib).
• Handle custom design simulations, use SPICE simulations and additional data to construct proprietary Timing models.
• Generate full chip timing model to bridge between IP timing models, using SPICE simulations or STA reports.
• FPGA power model know-how and knowledge will be added advantage.
• Experience with PrimeTime/Liberate will be added advantage.
• Additional Job Description 10 yrs experience of hardware integration design FPGA timing model know-how and knowledge will be added advantage.
• Successfully went through whole development from start to Tape Out of at least 2 products.
• Proficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.
• Working knowledge of System Verilog, synthesis, and static timing analysis.
• Specialist in floor-planning, power estimate, timing and back-end methodologies.
• Experience with Linux scripting and Python.
• Experience and knowledge of PnR is a plus.
• Strong written and oral communication skills.
• The ability to stay up-to-date with the latest advancements in technology & design.
• Ability to leverage AI tools to accelerate content creation, use AI to analyze large datasets and identify patterns.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in: Malaysia Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. At Lattice, our core values aren’t just something we look for in candidates – they’re something we actively cultivate and live by every day.

Lattice is strengthening is leadership in compute, communications, industrial, and embedded markets – underscored by multiple award wins that recognize its innovation, leadership, workplace culture, and collaboration-driven solutions.

Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader.

For over 40 years, Lattice has driven innovation in the semiconductor industry. Our compact, power-efficient field programmable gate arrays (FPGAs) are essential to building a secure, intelligent, and connected world.

Lattice is the #1 supplier of small FPGAs worldwide, with the largest installed base in the industry. Our solutions are trusted by over 11,000 customers globally, spanning the compute, communications, industrial, and embedded markets. Founded in 1983 in Oregon’s Silicon Forest, Lattice has grown into a global leader with a passionate team dedicated to pushing the boundaries of programmable logic and fostering a culture of innovation.

Headquartered in Portland, Oregon with major operations in San Jose, California, Shanghai, China, and Manilla, Philippines.

GROWTH

We foster a culture where everyone strives for continuous learning and development. We challenge ourselves to boldly deliver exceptional growth and value for customers and shareholders.

RELIABILITY

Our customers trust us to deliver, and we take that responsibility seriously. By committing ourselves to dependable supply, support, and solutions, we build strong collaboration that lasts and thrives.

EXECUTION

Innovation turns great ideas into results. Together, we create differentiated products and solutions through disciplined planning, decisiveness, and timely delivery with uncompromising quality.

ACCOUNTABILITY

We own our actions and outcomes: holding ourselves to the highest standards, agilely adapting to change, delivering on our commitments, and empowering each other to drive our success.

TRANSPARENCY

Openness builds trust. We lead with integrity and candor, facing hard facts and embracing tough conversations with clear communication, decisive action, and open honesty at every level.