Senior Staff/ Staff Design Verification Engineer/Architect

LATTICE SEMICONDUCTOR MALAYSIA SDN. BHD.; Penang; On-site; MYR 80,000 - 120,000; Full time

Job summary

A global developer of programmable logic solutions is seeking an experienced verification engineer in Penang, Malaysia. The ideal candidate will have over 8 years in digital design verification, including skills in HDL languages and automation scripting. Responsibilities include developing test strategies, performing detailed testing, and collaborating with IP architects. A competitive compensation and benefits program is offered.

Benefits

Comprehensive compensation and benefits program

Qualifications

• Minimum of 8 years experience in digital design verification.
• Proficient in debugging and analyzing complex digital designs.
• Experience with HDL languages and methodologies is essential.

Responsibilities

• Collaborate with IP architect to create verification strategies.
• Perform thorough testing of IP features.
• Develop automation scripts in Python and other languages.

Skills

Digital design verification experience

Debugging and analysis skills

HDL and HVL experience

Communication skills

Analytical skills

Automation scripting skills

Education

Bachelor or master’s degree in relevant field

Tools

Cadence IES/XCELIUM

Synopsys VCS

Mentor’s Questa

Job description

Lattice Semiconductor Malaysia Sdn. Bhd. is a global developer of low-cost, low-power programmable logic solutions.

Responsibilities

• Work with IP architect to understand IP features, create verification & testing strategies including testbench architecture and testplan.
• Perform detailed testing of IP features and ensure coverage is met.
• Ensure IP is compatible with industry standard synthesis & simulator tools.
• Coordinate with IP designer on IP release mechanism for testing.
• Develop scripts in Python and other scripting languages to automate soft IP development and testing process.

Qualifications

• At least 8 years digital design verification related experience.
• Bachelor or master’s degree in relevant field such as Electronics and Electrical Engineering, Computer Engineering, or Computer Science.
• Skill in debugging and analyzing complex digital design.
• Experience in HDL and HVL languages and methodologies such as SystemVerilog, UVM, OVM, Formal, SystemC.
• Knowledge in ASIC/FPGA/SoC verification or development cycle.
• Knowledge in simulation tools like Cadence IES/XCELIUM, Synopsys VCS, or Mentor’s Questa.
• Experience in building and deploying design verification related tools & methodologies.
• Experience in programming or scripting skills such as C++, Python, Perl, Shell, TCL or Make.
• Strong communication, analytical and documentation skills and ability to interface with other groups/site.
• Experience in industry standard protocols & technologies such as AMBA, Ethernet, PCIe, DRAM, Video, Security is a strong plus.

Lattice recognises that employees are its greatest asset and is committed to providing a comprehensive compensation and benefits program to attract, retain, motivate, reward, and celebrate the highest caliber employees.

Applications are welcome from all qualified candidates.