Senior Staff Engineer, Technology Development Engineering
ESSENTIAL DUTIES AND RESPONSIBILITIES:
- Drive NAND development from pre-silicon (circuit simulation for stress/screen test method), 1st silicon to qualification from DPPM (Defective part per million) perspective.
- Own and achieve DPPM targets in line with technology & product roadmaps.
- Develop and define test strategy and test flow for NAND technology on DOEs from dedicated Memory Health R&D line.
- Develop and define NAND silicon screen/stress strategy, algorithm, method, and spec as well as driving its effectiveness.
- Closely co-work with Fab technology development team to drive process improvement and countermeasure for failures revealed from MH R&D line.
- Collaborate with Flash BU (System/FW team) to develop error handling algorithms in system & firmware level.
- Work with PE/TE to come up with detail plans and drive for implementation on test flow, stress & screen developed from MH.
- Performing deep electrical failure analysis during new technology development and qualification phase. Define the action plans after communication with stockholders (Device engineer, Design engineers, Fab product engineer, etc.).
- Monitor memory health level and DPPM pareto for miscellaneous product lines. Work with FAB/device to improve and fine tune the fab process for DPPM reduction.
Qualifications
REQUIRED:
- Possessed master's degree or PhD in Electrical and Electronics engineering, Materials Science or any related discipline.
- Minimum 8 years of working experience with exposure in wafer level and reliability, DPPM and analysis.
- Deep understanding on electrical failure analysis methodology. Hands-on trouble shooting experience on memory products or system is preferred.
- Demonstrated ability to analyze problems, diagnose root cause, and apply corrective actions.
- Excellent data analysis skills including data crunching, parser automation, statistical analysis, and interpretation.
- Highly self-motivated, passionate about troubleshooting and solving complex problems.
PREFERRED:
- Semiconductor device physics
- Understanding of memory system and device FW
- Excellent English communication (written and verbal).
Skills
- DPPM evaluation and improvements.
- Failure analysis and resolution.
- Project management and technical leadership.
Additional Information
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