Senior FPGA IP Software Development Engineer

754 Altera Semiconductor Technology (M) Sdn. Bhd.; Seberang Perai; On-site; MYR 75,000 - 110,000; Full time

Job summary

A leading technology company in Penang is looking for a Senior FPGA IP Software Development Engineer. The role involves architecting and designing FPGA Soft IP cores, collaborating with cross-functional teams, and mentoring junior staff. Candidates should possess a strong background in algorithms and high-speed protocols, with significant experience in the field.

Qualifications

• 8+ years of experience in FPGA design.
• Strong experience with VHDL/Verilog/SystemVerilog.
• Hands-on experience with high-speed IP protocols.

Responsibilities

• Architect, design, and implement FPGA Soft IP cores.
• Collaborate with software and firmware teams for integration.
• Mentor junior engineers in RTL design and FPGA development.

Skills

VHDL

Verilog

SystemVerilog

IP packaging

CDC techniques

Static timing analysis

Memory-mapped register interfaces

Education

Bachelor’s or Master's degree in electrical/computer engineering

Tools

AMD Vivado

Intel Quartus

ModelSim

Questa

Job description

Senior FPGA IP Software Development Engineer page is loaded

Senior FPGA IP Software Development Engineer

Apply locations Penang 15, Penang, Malaysia time type Full time posted on Posted 8 Days Ago job requisition id R00829

Job Details:

Job Description:

• Architect, design, and implement FPGA Soft IP cores using VHDL/Verilog/SystemVerilog, targeting high-performance and resource-efficient implementations.

• Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.

• Develop parameterizable and reusable IP blocks for high-speed protocols (e.g., JESD204B/C, AXI, PCIe, Ethernet, DDR interfaces).

• Package IP cores with clearly defined interfaces, metadata, and configuration options for integration into vendor toolchains Quartus Platform Designer.

• Collaborate with software and firmware teams to define memory maps, register interfaces, and configuration protocols.

• Maintain and improve internal IP libraries, ensuring compliance with coding standards, documentation practices, and version control processes.

• Drive integration of IP into larger SoC or system-level FPGA designs, including handling timing closure and interoperability.

• Work closely with system architects and product managers to define IP requirements, performance targets, and roadmap features.

• Mentor junior engineers in best practices for RTL design, IP reuse, and FPGA development flows.

Qualifications:

• Bachelor’s or Master's degree in electrical/computer engineering or related field and 8+ years of experience.

• Strong experience with parameterizable RTL design using VHDL, Verilog, or SystemVerilog.

• Proficiency in IP packaging and integration using FPGA vendor tools such as AMD Vivado (IP Integrator), Intel Quartus (Platform Designer), or similar.

• Deep understanding of clock domain crossing (CDC) techniques, timing constraints (SDC/XDC), and static timing analysis (STA).

• Familiarity with bus protocols such as AXI4, Avalon, TileLink, and their use in IP design and integration.

• Hands-on experience with high-speed IP protocols, including familiarity withJESD204B/C, DDR3/DDR4, and memory or serial interface design considerations would be a plus.

• Experience building self-checking testbenches and automation of regression testing using tools like ModelSim, Questa, or XSIM.

• Knowledge of hardware-software interface design, including memory-mapped register interfaces and CSR frameworks.

• Experience with linting tools (e.g., SpyGlass, AscentLint) and synthesis/implementation constraints for FPGAs.

• Exposure to revision control (e.g., Git), issue tracking systems, and collaborative development workflows.

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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