PCIe System Validation Lead

Altera; Penang; On-site; USD 45,000 - 75,000; Full time

Job summary

Altera is seeking a System Validation Lead Engineer to develop and enhance test methodologies for high-speed PCIe validation. Join their innovative Platform Validation Team to work on cutting-edge technology, interfacing with design and architecture teams to ensure product excellence.

Qualifications

• Minimum 8 years of industry experience.
• Good knowledge in FPGA architecture/design/validation is an advantage.

Responsibilities

• Define and develop system validation environment and test suites for PCIe validation.
• Collaborate with teams to improve post-silicon test content.

Skills

Expertise in PCIe protocol

Creating test scripts

Understanding PCIe Link equalization algorithm

Knowledge in post silicon validation methodologies

Programming languages: tcl, python, C

Handling high speed test equipment

Education

BSEE/MSEE or equivalent

Job description

About the Company

Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation.

Our innovation of programmable logic started in 1983 in Silicon Valley. In 1984, Altera unveiled the world’s first programmable logic device capable of being programmed, erased, and reprogrammed altering the future of innovation.

As part of Altera, the Platform Validation Team plays a key role in both pre-silicon and post-silicon validation. We are responsible for validating all of Altera's products and solutions.

About the Role

We are looking for an enthusiastic System Validation Lead Engineer interested in working with Altera's latest cutting-edge technology.

Responsibilities

• Creates, defines and develops system validation environment and test suites for evolving PCIe protocol validation.
• Uses and applies system level tools and techniques to ensure functionality to spec.
• Responsible for the development of methodologies, execution of validation plans, and debug of failures.
• Requires broad understanding of high speed IP validation and requires interfacing with Architecture, design and IP teams.
• Collaborate with Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on die debug features.
• You will be involved in PCIe IP validation in the context of System level use cases for high-speed FPGA devices.
• In addition, drives exploration of IP validation methodology, platform and infrastructure enablement to improve process and efficiency.

Qualifications

• BSEE/MSEE or equivalent
• Minimum 8 years of industry experience

Required Skills

• Expertise in PCIe protocol (Gen3, Gen4, Gen5), PCIe Host systems, PCIe IP bring up and validation.
• Create test scripts for all validation purposes – Link disable/enable, Speed change, Resets and stability tests.
• Good understanding PCIe Link equalization algorithm, architecture and DFD.
• Good knowledge in post silicon validation methodologies and experience in handling PCIe protocol analyzer and processing the data dump.
• Good knowledge in FPGA architecture/design/validation is an added advantage.
• Experience in developing programming languages such as tcl, python, C-programming.
• Experience in handling various high speed test and measurement equipment such as ATE tester, high bandwidth real time/sampling oscilloscope, high frequency pulse/signal, power supplies.