PCIe/CXL Design Tech Lead

754 Altera Semiconductor Technology (M) Sdn. Bhd.; George Town; On-site; MYR 60,000 - 100,000; Full time

Job summary

An established industry player is seeking a PCIe/CXL Design Tech Lead to join their innovative team in Penang. This role involves developing cutting-edge PCIe/CXL solutions for next-generation FPGA technology. You will be responsible for RTL design and simulation, collaborating with IP providers, and ensuring design integrity. Ideal candidates will have extensive experience in micro-architecture and RTL coding, and a passion for high-speed serial interfaces. Join a dynamic team where your expertise will drive the future of technology in a supportive and collaborative environment.

Qualifications

• 7+ years experience in electrical/computer engineering or related field.
• 5+ years of RTL coding and IP integration experience.

Responsibilities

• Develop PCIe/CXL solutions for next-gen FPGA in latest process technology.
• Integrate and validate IPs at SoC level.

Skills

RTL Coding

PCIe/CXL Protocols

Micro-architecture Definition

Debugging Skills

Communication Skills

Education

Bachelor's Degree in Electrical/Computer Engineering

Master's Degree in Electrical/Computer Engineering

Tools

LINT

CDC

PT-STA

Fishtail

Power UPF

Job description

PCIe/CXL Design Tech Lead page is loaded

PCIe/CXL Design Tech Lead

Apply locations: Penang 15 Ecospace 1

Type: Full time

Posted on: Posted 8 Days Ago

Job requisition id: R00376

Job Details:

Job Description:

• Part of the global PCIe/CXL Center of Excellence (CoE) team, developing the latest & state-of-the-art PCIe/CXL solutions for next-generation FPGA in the latest process technology node.
• Develops logic/RTL design and simulation for IP/SoC design & integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design.
• Participates in defining PCIe/CXL architecture and microarchitecture features of the designed block. Collaborates with IP providers to integrate and validate IPs at the SoC level.
• Applies strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals, ensuring design integrity for physical implementation.
• Reviews verification plans and implementation to ensure correct feature verification, and implements corrective measures for RTL test failures to ensure feature correctness.
• Performs quality checks across various logic design aspects, from RTL to timing/power convergence, and drives quality assurance compliance for smooth IP/SoC handoff.

Qualifications:

• Bachelor’s degree in electrical/computer engineering or related field with 7+ years of experience, or a master’s degree with 6+ years of experience.
• Experience in micro-architecture (clocking, reset, power, etc.) definition & debugging. Good knowledge of PCIe/CXL or high-speed serial interfaces such as USB or Ethernet.
• 5+ years of RTL coding and/or IP integration experience into SoC design. Familiarity with design tools such as LINT, CDC, PT-STA, Fishtail, Power UPF, etc., and design concepts like data flow, algorithm state machines, finite state machines, and timing charts.
• Knowledge of FPGA background is a plus.
• Highly motivated team player with good communication skills.

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15

Additional Locations:

Ecospace 1

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, sex, national origin, ancestry, age, disability, medical condition, genetic information, military/veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by law.