Lead SerDes Digital Architect for 112G Ethernet & SoC Collaboration

Uni Connect; Penang; On-site; MYR 120,000 - 160,000; Full time

Job summary

A leading technology firm in Penang is seeking a veteran digital architect with extensive experience in high-speed SerDes design. The candidate will define digital micro-architecture, write high-quality RTL, and work closely with analog designers. This role requires a Master's degree in Electrical Engineering and over 10 years of hands-on experience along with deep skills in Verilog/SystemVerilog and DSP concepts. This is a unique opportunity to influence the architecture of cutting-edge technology.

Qualifications

• 10+ years of experience in architecting high-speed SerDes.
• Deep expertise in Verilog/SystemVerilog and synthesis.
• Solid grasp of DSP algorithms like FFE and DFE.

Responsibilities

• Define and document digital micro-architecture for PMA/PMD/PCS blocks.
• Write and verify high-quality Verilog RTL.
• Collaborate with analog designers to model mixed-signal effects.

Skills

Verilog/SystemVerilog

High-speed SerDes design

DSP concepts

Multi-clock-domain design

Synthesis and STA

Education

Master's degree in Electrical Engineering

Job description

A leading technology firm in Penang is seeking a veteran digital architect with extensive experience in high-speed SerDes design. The candidate will define digital micro-architecture, write high-quality RTL, and work closely with analog designers. This role requires a Master's degree in Electrical Engineering and over 10 years of hands-on experience along with deep skills in Verilog/SystemVerilog and DSP concepts. This is a unique opportunity to influence the architecture of cutting-edge technology.