Lead Analog IC Layout Engineer

Krisvconsulting Services Pte Ltd; Penang; On-site; MYR 120,000 - 160,000; Full time

Job summary

A leading consulting firm in Malaysia is seeking an experienced Analog Layout Engineer to lead IP/full-chip layout activities. The ideal candidate should have 9-14 years of experience in analog layout with proficiency in submicron CMOS techniques and strong knowledge of IR drop and EM analysis. This role involves utilizing Cadence Virtuoso and Mentor Calibre for layout verification and mentoring junior engineers. Competitive compensation and growth opportunities are offered.

Qualifications

• 9 -14 years of experience in analog layout with VLSI exposure.
• Proficient in submicron CMOS layout techniques.
• Strong knowledge of IR drop and EM analysis.
• Hands-on with Cadence Virtuoso and Mentor Calibre.

Responsibilities

• Lead or co-lead IP/full-chip layout activities from scratch.
• Perform floor planning, routing, and layout verification.
• Collaborate with cross-functional teams for seamless layout integration.
• Conduct internal and external layout design reviews.
• Troubleshoot layout issues and resolve violations efficiently.

Skills

Analog Layout

VLSI exposure

Submicron CMOS layout techniques

IR drop analysis

EM analysis

Problem-solving

Analytical abilities

Effective communication

Teamwork skills

Education

Bachelor's Degree in Electrical / Electronic Engineering or Physics

Tools

Cadence Virtuoso VXL

Mentor Calibre

Job description

Seeking an experienced Analog Layout Engineer with a Bachelor's Degree in Electrical / Electronic Engineering or Physics, to lead and execute IP/full-chip layout from planning to verification, ensuring high-quality and on-time delivery.

Key Responsibilities:

• Lead or co-lead IP/full-chip layout activities from scratch.

• Perform floor planning, routing, and layout verification (LVS, DRC, Antenna checks).

• Collaborate with cross-functional teams for seamless layout integration.

• Conduct internal and external layout design reviews.

• Utilize CAD tools (Cadence Virtuoso VXL, Mentor Calibre) for layout and checks.

• Troubleshoot layout issues and resolve violations efficiently.

• Mentor and guide junior engineers to ensure quality and delivery.

• Drive layout optimization and methodology improvement.

Required Skills:

• 9 -14 years of experience in analog layout with VLSI exposure.

• Proficient in submicron CMOS layout techniques.

• Strong knowledge of IR drop and EM analysis.

• Hands-on with Cadence Virtuoso and Mentor Calibre.

• Excellent problem-solving and analytical abilities.

• Effective communicator with initiative and teamwork skills.

• Experience in analog layout from scratch.

• Capable of working across functions and teams.