IP Design Engineer

Lattice Semiconductor; Penang; On-site; MYR 100,000 - 150,000; Full time

Job summary

Lattice Semiconductor seeks an experienced IP Design Engineer in Penang. The role focuses on designing high-speed RTL for Connectivity IP portfolios while collaborating with architects. Candidates should possess a background in FPGA design and relevant programming skills, aiming to thrive in a dynamic environment.

Qualifications

• Minimum of 5 years FPGA IP design experience.
• Independent and self-motivated.
• Capable of executing in a dynamic environment.

Responsibilities

• Build Connectivity IP portfolios for Lattice FPGA.
• Translate specifications into high-speed RTL design.
• Optimize for performance, power, and logic utilization.

Skills

High-speed SERDES protocols

FPGA RTL design

Logic verification

C/C++ programming

Python

Education

BS/MS/PhD in Electronics or Computer Engineering

Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast-paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

We are seeking an IP Design engineer, passionate individual with technical leadership capabilities to build Connectivity IP portfolios for Lattice FPGA. The individual should have the ability to work closely with architects to translate specifications into high-speed RTL design, optimizing for performance, power, and logic utilization.

Requirements

Key Skills

• Experience in high-speed SERDES protocols (e.g., PCIe, Ethernet, CPRI, JESD204B/C) or Peripherals (SPI, I2C, I3C) or Interconnect (AXI, AHB, APB) is a plus.
• Hands-on experience in FPGA RTL design, logic verification, debugging, and timing closure are preferred.
• Programming skills (e.g., C/C++, Perl, TCL, Python).
• Experience in hardware validation or hardware interoperability testing is a plus.
• Experience in soft IP packaging, example design, and testbench development is an advantage.

Education and General

• BS/MS/PhD in Electronics or Computer Engineering with a minimum of 5 years of FPGA IP design experience.
• Independent and self-motivated, capable of executing in a dynamic environment with uncertainties.