Digital IC Design Backend Manager

JAC Recruitment; Kuala Lumpur; On-site; MYR 120,000 - 180,000; Full time

Job summary

A rapidly growing IC design platform company is seeking a Digital Backend IC Design Manager in Kuala Lumpur. Join a skilled team to handle complex backend tasks, collaborate on innovative projects in High-Performance Computing, AI, and Automotive sectors. Ideal candidates have extensive IC design experience with a Bachelor's degree in Microelectronics.

Benefits

Competitive annual remuneration package

Attractive allowances

Dynamic team environment

Transparent and open work culture

Qualifications

• Over 7 years of relevant work experience required.
• Comprehensive knowledge in the IC design process from Netlist to GDS.
• Proficient in top-level Place and Route tasks.

Responsibilities

• Perform digital backend tasks including Place and Route, Static Timing Analysis, and Physical Verification.
• Collaborate with front-end engineers to resolve design issues.
• Execute moderate to high complexity Physical Design work.

Skills

Design process knowledge

Static Timing Analysis

Place and Route expertise

Troubleshooting skills

Experience with high-speed interfaces

Education

Bachelor's degree in Microelectronics

Tools

Innovus

ICC2

StarRC

PTPX

Job description

Company and Job Overview
A rapidly growing IC design platform company specializing in IP, SOC, and ASIC design services is seeking a talented and experienced Digital Backend IC Design Manager. Become part of a team of highly skilled engineers and designers who provide exceptional support to customers in High-Performance Computing, AI, 5G & Networking, and Automotive industries, utilizing cutting-edge technology.

Key Responsibilities

• Perform comprehensive digital backend tasks from netlist to GDS, at both the TOP and block levels, including Place and Route (PR), Static Timing Analysis (STA), Physical Verification (PV), Power Analysis (PA), and related activities.
• Collaborate closely with digital front-end engineers to troubleshoot and resolve issues such as timing discrepancies, SDC constraints, and UPF challenges.
• Execute block-level or Top-level Physical Design (PD) work of moderate to high complexity.
• Handle pre-mask and post-mask Engineering Change Orders (ECOs) efficiently.

Key Requirements

• Bachelor's degree or higher in Microelectronics or a related field, with over 7 years of relevant work experience.
• Comprehensive knowledge and experience in the complete design process, from Netlist to GDS.
• Proficient in one or more design tools, such as Innovus/ICC2, PT/Computers, LEC/Form, StarRC/QRC, PTPX/Volt, Caliber, etc.
• Preferred experience in successfully completing chip tape-outs with process sizes below 14nm, especially low-power design chips.
• Strong expertise in Top-level Place and Route (P&R) work, including tasks such as top-level partitioning, bump assignment, RDL routing, ESD planning, feedthrough insertion, and pin assignment.
• Priority consideration for candidates with proven Top-level Static Timing Analysis (STA) experience.
• Experience in Place and Route (P&R) for high-speed interfaces such as PCIE and DDR is highly desirable.

Benefit

• Competitive annual remuneration package complemented by attractive allowances
• Dynamic team composed of a vibrant workforce.
• Transparent and open work environment fostering collaboration and trust.