Digital Backend Design Engineer (Chip Design)

Wikicareer Sdn. Bhd.; Kuala Lumpur; On-site; MYR 80,000 - 110,000; Full time

Job summary

A semiconductor solutions company based in Kuala Lumpur is seeking a Backend Design Engineer. The role involves leading chip floorplanning, executing backend implementation flows, and collaborating with cross-disciplinary teams. Candidates should possess a relevant degree and have substantial experience with EDA tools. Strong problem-solving and communication skills are crucial for success in a team-oriented environment.

Qualifications

• 3–5 years of relevant backend/physical design experience preferred.
• Hands-on experience with EDA tools is required.
• Strong knowledge in timing closure and signal integrity is essential.

Responsibilities

• Lead chip floorplanning and optimization.
• Execute the full backend digital implementation flow.
• Perform Place & Route (P&R), Clock Tree Synthesis (CTS), and Static Timing Analysis (STA).

Skills

Backend/physical design expertise

Strong teamwork

Analytical problem-solving

Communication skills

Education

Bachelor’s or Master’s degree in Integrated Circuits, Microelectronics, Electronics, Electrical/Communications Engineering

Tools

Cadence Innovus

Synopsys ICC2/PrimeTime

Mentor Calibre

Job description

Overview

Our client are a semiconductor chip design and system solutions provider, delivering end-to-end services from RTL and analog design to backend implementation, verification, and system integration. The teams collaborate with global clients to design and implement advanced ASICs/SoCs across consumer, automotive, industrial, and IoT applications.

Responsibilities

• Lead chip floorplanning and optimization to ensure efficient area utilization and performance.

• Execute the full backend digital implementation flow (Netlist → GDSII) using industry-standard EDA tools (Cadence, Synopsys, Mentor/Siemens).

• Perform Place & Route (P&R), Clock Tree Synthesis (CTS), Static Timing Analysis (STA), and design optimization for timing, power, and area (PPA).

• Conduct power integrity checks, IR drop and crosstalk analysis, and sign-off verification (DRC/LVS).

• Work closely with front-end RTL, analog/mixed-signal, and verification teams to ensure smooth integration and closure of top-level designs.

• Support system-level integration projects, aligning backend implementation with overall chip and system solution requirements.

• Prepare and maintain backend design specifications, reports, and technical documentation for client delivery.

Qualifications

• Bachelor’s or Master’s degree in Integrated Circuits, Microelectronics, Electronics, Electrical/Communications Engineering, or related field.

• Proven expertise in backend/physical design flows for ASIC/SoC implementation.

• Hands-on experience with EDA tools (e.g., Cadence Innovus, Synopsys ICC2/PrimeTime, Mentor Calibre).

• Strong knowledge of timing closure, power analysis, and signal integrity methodologies.

• Prior experience in top-level chip backend design is highly desirable.

• Excellent teamwork and communication skills, with ability to collaborate across multidisciplinary chip design teams.

• Analytical, problem-solving mindset with strong learning agility.

• 3–5 years of relevant backend/physical design experience preferred.