Design Verification Manager

Lattice Semiconductor; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

A leading semiconductor company seeks a Senior FPGA Design Verification Engineer to join its Silicon Engineering team in Malaysia. This role involves leading complex verification projects, requiring extensive experience in FPGA design, SystemVerilog, UVM methodologies, and strong teamwork. Ideal candidates will have an established track record in managing teams and solving intricate verification challenges.

Qualifications

• 8+ years of hands-on FPGA/SOC ASIC DV experience.
• 5 years leading a DV team for complex FPGA/ASIC.
• Proven track record from concept to tape-out.

Responsibilities

• Lead the verification of complex FPGAs and ASICs.
• Create reusable UVM test benches and improve tape-out readiness.
• Collaborate across teams for comprehensive verification.

Skills

FPGA Design Verification

SystemVerilog

UVM methodology

C/C++ programming

Perl/Python/Tcl

Debugging

Education

BS or MS in Electrical/Computer Engineering or related field

Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities & Skills

Inviting candidates with a passion for invention and self-challenge. This position offers an opportunity to be part of cutting-edge projects within Lattice’s Silicon Engineering team. You will lead and contribute to verifying complex FPGAs, integrating multiple IP-level Design and Verification (DV) environments, crafting reusable UVM test benches, implementing coverage-driven test cases, deploying new tools, and improving tape-out readiness. Collaborating across teams, you will push industry boundaries of FPGA systems and enhance our product for global customers. You will learn about FPGA architectures, high-speed protocols, low-power methodologies, DV best practices, verification on accelerated platforms, serial protocols, FW-HW interactions, and FPGA/SOC debug architectures. This role is central to our silicon verification efforts, requiring proficiency across FPGA design verification domains, thriving in dynamic, multi-disciplinary teams, and solving complex problems with advanced methodologies.

Description

Understand various protocol technologies such as DDR SDRAM, AMBA interconnects, Ethernet, Video (DisplayPort, MIPI, HDMI, SDI), JESD204B, PCIe. Develop verification plans from specifications, review and refine to meet coverage targets. Create IP-level modules, sub-system verification plans, test benches, sequences, and infrastructure. Architect reusable UVM test benches, integrate VIPs, and coordinate with design, architecture, software, firmware, and external IP teams to verify FPGA designs comprehensively.

Key Qualifications

• BS or MS in Electrical/Computer Engineering, Computer Science, or related field
• 8+ years of hands-on FPGA/SOC ASIC DV experience
• At least 5 years leading a DV team verifying complex FPGA/ASIC
• Proven track record from concept to tape-out and silicon bring-up
• Expertise in SystemVerilog and UVM methodology
• Programming skills in C/C++, Perl/Python/Tcl for automation
• Experience verifying subsystems like DDR SDRAM, AMBA, Ethernet, Video interfaces, JESD204B, PCIe
• Knowledge of low power design, UPF, boot-up, HW/FW interaction verification
• Hardware validation and debugging experience is a plus

As a manager, should be a great team leader with strong interpersonal, communication, and problem-solving skills, and a desire for diverse challenges.