Custom Layout Engineer

AdoreSys; Bayan Lepas; On-site; MYR 60,000 - 120,000; Full time

Job summary

AdoreSys in Penang, Malaysia seeks a Custom Layout Engineer to drive physical implementation of Foundation IP, Memory/IO/ESD, Analog IP and RF building blocks.

You will own floorplanning, layout construction, physical verification and QA sign-off, and collaborate with multi-site teams to optimize Power, Performance & Area for complex projects.

This role offers a clear path to senior positions within a fast-paced, innovative semiconductor environment.

Qualifications

• Bachelor’s degree in Electrical, Electronic, or Materials Engineering.
• 2–7 years of hands-on experience in custom IC layout for Standard Cell/Memory/IO-ESD.
• Understanding of DRM for advanced CMOS tech and DFM issues in high-performance layouts.
• Proficient in debugging physical verification checks (DRC/LVS/ERC, etc.).
• Proficient with Synopsys/Cadence layout editors and physical verification tools.
• Strong cross-team communication and time management.
• Experienced candidate may be considered for senior position.

Responsibilities

• Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP, and RF building blocks.
• Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning, layout construction, physical verification and QA flow sign-off.
• Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery for each project.
• Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area (PPA).

Skills

Deep CMOS DRM understanding

DFM considerations

Analytical debugging

Cross-team communication

Time management

Team player

Education

Bachelor’s degree in Electrical/Electronic/Materials Engineering

Tools

Synopsys/Cadence layout editors

Physical verification tools

Job description

Level: Junior/Senior/Staff/Technical Lead

Location: Penang, Malaysia

Overview:

Are you passionate about driving innovation in microchip design? Ready to take the lead in shaping the next generation of integrated circuits? We’re looking for a variety of positions for Custom Layout Engineer to join our team and make a significant impact on advanced semiconductor technology—including the chips powering tomorrow’s AI breakthroughs.

What you’ll do:

• Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP, and RF building blocks.
• Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning, layout construction, physical verification and QA flow sign-off.
• Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery for each project.
• Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area (PPA).

Who we’re looking for:

• Bachelor’s degree in Electrical, Electronic, or Material Science Engineering.
• More than 2~7 years of hands-on experience in custom IC layout for Standard Cell, Memory Compiler or IO/ESD libraries using advanced finFET/GAA process nodes; candidates with Analog/RF experiences are welcomed to apply.
• Proficient in understanding DRM of advanced CMOS technologies and have a good grasp of deep sub-micron and DFM issues for high-performance layout designs.
• Analytical and skillful in debugging physical verification checks (eg. DRC/LVS/ERC, etc.).
• Proficient in Synopsys/Cadence layout editor and physical verification tools.
• Team player and effective in cross-team communication and time management.
• Experienced candidate will be considered for senior position.