AI-Powered Front-End Implementation Engineer

UST; Bayan Lepas; On-site; MYR 90,000 - 130,000; Full time

Job summary

UST is seeking a Front-End Implementation Engineer specialized in AI-driven silicon design. You will develop AI agents to automate front-end tasks, integrate AI workflows, and validate results against manual reviews in a multi-tool EDA environment.

The role requires experience with Verilog/SystemVerilog, RTL-to-netlist flow, and strong Python/Tcl scripting. Collaboration across multi-site teams and exposure to cloud AI platforms are expected.

Qualifications

• 3+ years of experience in front-end implementation (synthesis, static timing analysis, CDC/RDC/LINT, or low power) or in EDA flow and tool development.
• 1+ year of practical experience applying AI/ML or Generative AI technologies.
• Working knowledge of Verilog/SystemVerilog and the RTL-to-netlist flow.

Responsibilities

• Develop AI agents and skills that automate front-end implementation tasks: run launch and monitoring, QoR and area/timing regression reporting, constraint and waiver review, and timing debug.
• Apply LLMs and agentic AI to automate tasks such as synthesis timing violation root-cause analysis, CDC/LINT waiver triage, UPF comparison, netlist quality review, and regression failure analysis.
• Build AI-powered engineering workflows using Python, MCP, agent frameworks, vector databases and modern GenAI platforms.
• Support front-end flow execution: launch power-aware synthesis runs, generate and check constraints, run CDC/RDC/LINT and netlist quality checks, and prepare the results for engineering review.
• Package and document AI skills and agents so that other engineers can reuse them, and publish them to the team's shared repository.
• Work with front-end engineers to identify repetitive tasks worth automating, and validate that automated results match manual review.
• Report progress, results, and the measured time savings of the workflows delivered.

Skills

Front-end implementation

AI/ML technologies

Python scripting

Tcl scripting

Git usage

Linux scripting

Education

BS or above in Electrical Engineering / Microelectronics / IC Science / Computer Engineering / Computer Science

Major in Micro-Electronics or Computer Science

Tools

Verilog/SystemVerilog

RTL-to-netlist flow

Fusion Compiler

PrimeTime

Formality/Conformal LEC

VSI/VCLP

SpyGlass/0-In

Job description

UST is seeking a Front-End Implementation Engineer specialized in AI-driven silicon design. You will develop AI agents to automate front-end tasks, integrate AI workflows, and validate results against manual reviews in a multi-tool EDA environment.

The role requires experience with Verilog/SystemVerilog, RTL-to-netlist flow, and strong Python/Tcl scripting. Collaboration across multi-site teams and exposure to cloud AI platforms are expected.