WLAN RTL Design-Sr Engineer

Qualcomm; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Benefits offered by this job

Disability accommodations available

Equal opportunity employer

Job summary

Qualcomm India Private Limited is seeking a hardware engineer to develop WLAN hardmacros at block/IP and system levels, across 6nm and beyond. You will apply power-aware synthesis, timing constraints, and validation, collaborating with CAD, IP and design teams to meet timing goals.

The role emphasizes mentoring junior engineers, scripting for automation, and leading initiatives in front-end implementation tool flows. Strong communication across global teams is essential.

Qualifications

• Bachelor's or Master's in Electrical Engineering or related field.
• 8 years of experience in SOC logic synthesis and timing constraints.
• Strong expertise in STA timing analysis basics and related concepts.

Responsibilities

• Implement next generation WLAN hardmacro at block/IP and system level.
• Work on physical and power aware synthesis, constraints generation and validation.
• Collaborate with physical design, CAD, IP and Design Technology teams.
• Mentor junior team members and lead small groups on projects.
• Handle ECOs manually or with conformal ECO tooling where required.

Skills

Synthesis

Timing analysis

STA timing

Scripting (tcl/perl)

Team leadership

Problem solving

Communication

Education

Electrical Engineering

Computer Science/Engineering

Master's in Engineering

PhD in Engineering

Tools

DCG/FC/Genus

Primetime

Formality/LEC

Conformal

Ptpx/Power Artist

Tempos

Job description

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Job Overview

• Candidate will be responsible for next generation WLAN hardmacro implementation
• The candidate will work with best-in-class methodologies, tools and technology to design innovative WLAN products at the block/IP-level and at system-level in 6nm and beyond (process technologies).
• This role will require the candidate to work on physical and power aware synthesis, logic equivalence, constraints generation & validation, static timing analysis
• Optimize data path design for low-area, low-power and high-speed using advanced features in synthesis such as MCMM, SAIF, multibit mapping etc.
• You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation.
• Should be able to work on netlist level ECOs manually or with conformal ECO tool.
• The candidate should also possess automation skills and be well versed in scripting languages
• The candidate should be able to mentor junior members of the team.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Minimum Qualifications

• Bachelor’s or Master’s in Electrical Engineering or related field
• 8 years of experience in SOC logic synthesis and timing constraints

Preferred Qualifications

• Must hold a Bachelor’s and/or a Master’s in Electrical Engineering with at least 8+ years’ experience in SOC logic synthesis and timing constraints
• Experience required in one or more tools/areas: Synthesis (DCG/FC/Genus), Formal Verification (LEC/Formality), STA (Primetime)
• Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
• Hands-on experience with STA tools - Prime-time, Tempus
• Have experience working on timing convergence at Chip-level and Hard-Macro level.
• Good understanding of timing constraints development
• Good understanding low power and power simulations using ptpx/power artist/conformal low power
• Could be substituted for experience in Physical Design or Circuit Design, with eagerness to learn front-end implementation tool flows
• Should have good analytical ability, problem solving skills and be a self-starter
• Candidate should be able to lead and work in a team environment
• Good scripting skills using tcl/perl languages
• Strong communication skills to work with design teams worldwide
• Familiarity with the following is a plus, but not required : Digital Communications, LTE/802.11 protocols

Keywords

Synthesis, Implementation , ASIC, STA, PD, Formal Verification, UPF, CLP, Primetime, Backend

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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