Tech Lead– Verification Methodology/CAD

Linuxconfig; India; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Astera Labs is seeking a Tech Lead – Verification Methodology/CAD/Automation Engineer to drive scalable verification infrastructure and productivity across IP/SoC teams. You will build reusable methodologies, automate workflows, and partner with design verification to improve coverage and signoff.

The role requires 6–12 years of experience in verification, CAD, and automation, with strong SystemVerilog/UVM knowledge and experience with VCS/Xcelium/Questa. On-site India role with mentoring duties.

Qualifications

• Experience in verification methodology, CAD, and automation.
• Strong programming/scripting in Python, Tcl, Perl, Shell; C/C++ preferred.
• Strong understanding of SystemVerilog/UVM used in IP/SoC verification.
• Experience with simulation tools such as VCS, Xcelium, Questa.
• Experience building and maintaining regression infrastructure.
• Knowledge of coverage collection and analysis in complex projects.
• Familiarity with verification workflows: Simulation, UVM, Lint, CDC/RDC, Formal, regression, debug.

Responsibilities

• Own verification methodology and infrastructure across projects.
• Develop scalable frameworks for simulation, regression, coverage, and signoff.
• Build and maintain verification CAD/automation flows.
• Develop automation scripts and tools (Python, Tcl, Perl, Shell, C/C++).
• Automate test generation, regression execution, results collection, and reporting.
• Improve turnaround time via parallelization and optimization.
• Integrate tools into common verification workflows and dashboards.

Skills

Verification methodology

CAD

Automation

Python

Tcl

Perl

Shell

C/C++

SystemVerilog/UVM

Simulation tools (VCS/Questa/Xcelium)

Regression infrastructure

Coverage analysis

Verification flows (Simulation/UVM/Lin

Education

B.E./B.Tech/M.E./M.Tech in Electronics/EE/CS/CE/VLSI

Tools

VCS

Xcelium

Questa

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

TechLead– Verification Methodology / CAD / Automation Engineer

Experience - 6–12years

Job Summary

We are looking for a Tech Lead – Verification Methodology/CAD/Automation Engineer to drive verification infrastructure,methodology, automation, and productivity across IP and SoC verification teams.

The candidate will build scalable verification frameworks, automate verification workflows, improve regression infrastructure, and partner with design verification teams toestablishefficient and reusable methodologies.

Key Responsibilities

• Own and drive verificationmethodologyand infrastructure across projects.
• Develop scalable frameworks for simulation, regression, coverage, debug, and verification signoff.
• Build andmaintainverification CAD/automation flows .
• Develop automation scripts and tools using Python,Tcl, Perl, Shell , and/or C++.
• Automate test generation, compilation, regression execution, result collection, coverage analysis, and reporting.
• Improve simulation and regression turnaround time through parallelization and optimization.
• Integrate simulation, lint, CDC/RDC, formal, coverage, and other verification tools into common workflows.
• Develop dashboards and metrics forverificationquality, coverage, regression health, and project status.
• Debug infrastructure and tool-flow issues and provide rapid support to verification teams.
• Establish reusable verification components, scripts, libraries, andmethodologyguidelines.
• Drive adoption of best practices across multiple verification teams.
• Evaluate new verification technologies and tools and recommend improvements.
• Work closely with EDA vendors to troubleshoot tool issues and improve flows.
• Support migration and integration of new EDA tool versions and methodologies.
• Develop documentation and training for verification teams.
• MentorverificationCAD/methodologyengineers and provide technical leadership.

Required Technical Skills

• Strong experience in verificationmethodology, CAD, and automation .
• Strong programming/scripting skills in Python,Tcl, Perl, Shell , and preferably C/C++.
• Strong understanding of SystemVerilog/UVM .
• Experience with simulation tools such as VCS,Xcelium, Questa , or equivalent.
• Experience building andmaintainingregression infrastructure.
• Strong knowledge of coverage collection and analysis.
• Understanding of verification flows including:
• Simulation
• UVM
• Lint
• CDC/RDC
• Formal
• Code/functional coverage
• Regression
• Debug
• Excellent automation and problem-solving skills.

Preferred Experience

• Experience with large-scale SoC/IP verification environments .
• Experience integrating multiple EDA tools into a unified verification flow.
• Experience with CI/CD infrastructure such as Jenkins, GitLab CI, or equivalent .
• Experience with distributed/parallel regression infrastructure.
• Experience with cloud-based or scalablecomputeenvironments.
• Knowledge of databases, dashboards, APIs, or web-based verification infrastructure is an advantage.
• Experience working with EDA vendors and managing tool-flow issues.
• Act as the technical owner forverificationmethodologyand automation.
• Identifyopportunities to improve verificationproductivity, quality, and turnaround time .
• Define and enforceverificationmethodologystandards.
• Mentor engineers and drive adoption of common frameworks.
• Work across multiple projects and teams to solve infrastructure challenges.
• Strong ability to balance immediate project requirements with long-termmethodologyimprovements.

Education

B.E./B.Tech/M.E./M.Techin Electronics, ElectricalEngineering, Computer Science, Computer Engineering, VLSI , ora relateddiscipline.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.