SystemC Design Engineer

Chipsolve Technologies

Hyderabad

On-site

INR 1,500,000 - 2,500,000

Full time

8 days ago

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Job summary

Chipsolve Technologies in Hyderabad, India seeks a SystemC Design Engineer to develop and maintain SystemC-based models for hardware/IP/SoC systems. The role emphasizes SystemC modeling, C++ programming, and understanding of digital design concepts, with collaboration across RTL, verification and architecture teams.

Ideal candidates will have hands-on SystemC experience and a strong debugging mindset, applying TLM-2.0 techniques to transactional models and architecture exploration.

Qualifications

  • Strong programming experience in C++.
  • Hands-on experience with SystemC.
  • Good understanding of digital design / hardware / SoC concepts.
  • Good problem-solving and debugging skills.

Responsibilities

  • Develop and maintain SystemC models for IP, SoC and hardware components.
  • Develop transaction-level and architectural models using SystemC/TLM.
  • Develop, debug and optimize C++/SystemC models.
  • Analyze model performance, functionality and accuracy.
  • Collaborate with RTL, verification and architecture teams.
  • Debug issues across SystemC/C++ models and hardware/RTL environments.

Skills

C++
SystemC
Digital design
Problem solving

Job description

Job Description

We are looking for a SystemC Design Engineer with strong C++ and digital/SoC design knowledge to develop and maintain SystemC-based models for hardware/IP/SoC systems.

The ideal candidate will have hands-on experience in SystemC modeling, C++, TLM/TLM-2.0, and good understanding of hardware design concepts. Experience with Verilog/SystemVerilog and SoC/IP modeling is highly desirable.


Must Have Skills
  • Strong programming experience in C++.
  • Hands-on experience with SystemC.
  • Good understanding of digital design / hardware / SoC concepts.
  • Good problem-solving and debugging skills.

Key Responsibilities
  • Develop and maintain SystemC models for IP, SoC and hardware components.
  • Develop transaction-level and architectural models using SystemC/TLM.
  • Develop, debug and optimize C++/SystemC models.
  • Analyze model performance, functionality and accuracy.
  • Collaborate with RTL, verification and architecture teams.
  • Debug issues across SystemC/C++ models and hardware/RTL environments.
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