Staff / Sr. Staff Engineer DV

SiFive India Private Limited; Bengaluru; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

SiFive India Private Limited in Bengaluru is seeking an experienced engineer to lead the verification and optimisation of RISC‑V Low Power Profiles. The ideal candidate will have over 7 years of experience in power management, a strong background in UVM test-bench development, and hold a relevant degree.

The role involves collaborating with design teams, achieving quality-closure targets, and providing mentorship. We encourage applicants who are committed to fostering diversity and an inclusive environment.

Qualifications

• 7+ years of experience in low-power, power-aware or power-management.
• Hands-on UVM test-bench development.
• Experience leading efforts and driving multiple projects.

Responsibilities

• Lead the verification and optimisation of RISC‑V Low Power Profiles.
• Drive and achieve quality-closure targets at CPU and block levels.
• Collaborate closely with microarchitecture and RTL design teams.

Skills

Low-power, power-aware or power-management

UVM test-bench development

Power simulation on VCS and UPF

Script writing in Python, Perl or TCL

Problem-solving skills

Education

Bachelor's or Master's in Electrical & Electronic Engineering, Electrical & Communication Engineering, or VLSI

Job description

About SiFive: As the pioneers who introduced RISC‑V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC‑V to the highest performance and most data‑intensive applications. SiFive’s unrivaled compute platforms enable leading technology companies worldwide to innovate, optimise, and deliver advanced solutions across all sectors of chip design, including AI, ML, automotive, data centre, mobile, and consumer. With SiFive, the future of RISC‑V has no limits.

Key Responsibilities

• Lead the verification and optimisation of our diverse RISC‑V Low Power Profiles, including UPF.
• Drive and achieve quality‑closure targets at both CPU and block levels.
• Collaborate closely with microarchitecture and RTL design teams to optimise complex power flows.
• Provide technical leadership and mentorship to junior team members to foster growth.
• Actively participate in test planning and execution for new architecture and design features.

Requirements

• 7+ years of experience in low‑power, power‑aware or power‑management.
• Hands‑on UVM test‑bench development.
• Experience in core micro‑architecture (highly desirable).
• Experience leading effort and driving multiple projects.
• Experience with power simulation on VCS and UPF.
• Experience with script writing in Python, Perl or TCL.
• Experience with power impact at architecture, logic, and circuit levels.
• Excellent problem‑solving skills and ability to work in a dynamic, diverse environment.

Qualification

A minimum of a bachelor’s or master’s degree, or equivalent, in Electrical & Electronic Engineering, Electrical & Communication Engineering, or VLSI with consistently good academics.

Additional Information

This position requires successful background and reference checks and satisfactory proof of right to work in India. Any offer of employment is contingent on verifying your authorisation to access export‑controlled technology under applicable export‑control laws or obtaining necessary export licences/approvals.

SiFive is an equal‑opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.