Staff Engineer, STA

Renesas; Bengaluru; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Renesas is seeking a Senior/Staff STA Engineer in Bengaluru to ensure timing closure for block- and full-chip designs. You will own timing constraint development, perform setup/hold and variation-aware analyses, and collaborate with PD, RTL, Synthesis, and Signoff teams to drive ECO-based optimizations through tapeout.

The role requires strong experience in CMOS timing, SDC management, and industry STA tools, with scripting skills in Tcl, Python, or Perl.

Qualifications

• Experience with STA across modes and corners.
• Strong understanding of CMOS fundamentals and timing concepts.
• Hands-on analysis of setup/hold, path-based and derates.
• Familiarity with SDC, false paths and multicycle paths.
• Experience with ECOs and timing closure methodologies.
• Ability to work cross-functionally with PD, RTL, and Signoff teams.

Responsibilities

• Perform full-chip and block-level STA across modes/corners.
• Debug timing violations including setup/hold and clock-gating issues.
• Collaborate with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
• Develop and validate timing constraints and signoff readiness (SDC creation).
• Drive timing closure through ECOs and timing optimization.
• Analyze timing impact of PVT variations and support pre/post-layout signoff.

Skills

Static Timing Analysis

Timing closure

CMOS fundamentals

Setup/Hold analysis

Clock tree/uncertainty

SDC/timing exceptions

Debugging timing violations

Team collaboration

Tools

Synopsys PrimeTime

Cadence Tempus

Tcl scripting

Python scripting

Job description

Staff Engineer, STA

Job Description

Senior/Staff STA (Static Timing Analysis) Engineer

The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tapeout.

What you’ll do

• Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
• Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
• Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
• Drive timing closure through ECO implementation and timing optimization.
• Analyze timing impact due to process, voltage, and temperature variations.
• Support timing signoff for pre-layout and post-layout stages.
• Perform cross-functional reviews for timing convergence and provide recommendations.
• Generate timing reports and communicate closure status to project stakeholders.

Qualifications

What we’re looking for

• 4–12 years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs.
• Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.
• Hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
• Good understanding of clock tree, clock uncertainty, latency, skew, and jitter.
• Experience in timing constraints development and debugging.
• Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
• Familiarity with timing closure techniques and ECO methodologies.
• Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Good scripting skills in Tcl, Perl, or Python.
• Ability to analyze and resolve timing violations independently.

Nice to have

• Exposure to low-power timing analysis and UPF/CPF-aware STA.
• Familiarity with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure.
• Knowledge of advanced technology nodes and variation-aware signoff methodologies.
• Exposure to automation and flow development.
• Experience in cross-functional collaboration with PD, RTL, and Signoff teams.

Company Description

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier .

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement (https://jobs.renesas.com/diversity-and-inclusion) .

1. Department Manufacturing
2. Location Bengaluru
3. Remote No