Staff Engineer, STA and Synthesis

Renesas Electronics; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Competitive benefits package

Job summary

Renesas Electronics in Bengaluru seeks a seasoned STA Engineer to own timing closure for block and full-chip designs across modes and corners. You will craft timing constraints, validate signoff readiness, and collaborate with Synthesis, Physical Design and Design teams to optimize ECO-driven timing improvements.

The ideal candidate brings 7–10 years of experience, strong CMOS knowledge and hands-on experience with PrimeTime or Tempus, plus scripting in Tcl/Perl/Python to streamline flows.

Qualifications

• 7–10 years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs.
• Strong understanding of CMOS fundamentals, timing concepts and semiconductor design flow.
• Hands-on setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
• Good understanding of clock tree, clock uncertainty, latency, skew and jitter.
• Experience in timing constraints development and debugging.
• Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
• Familiarity with timing closure techniques and ECO methodologies.
• Hands-on experience with toolchains like PrimeTime or Tempus.
• Good scripting skills in Tcl, Perl, or Python.
• Ability to analyze and resolve timing violations independently.
• Nice-to-have: UPF/CPF-aware STA, SI-aware timing, Crosstalk analysis, and variation-aware signoff.

Responsibilities

• Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity timing violations.
• Collaborate with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
• Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
• Drive timing closure through ECO implementation and timing optimization.
• Analyze timing impact due to process, voltage, and temperature variations.
• Support timing signoff for pre-layout and post-layout stages.
• Conduct cross-functional reviews for timing convergence and provide recommendations.
• Generate timing reports and communicate closure status to project stakeholders.

Skills

Static Timing Analysis (STA)

Timing closure

SDC & timing constraints

PrimeTime / Tempus

Scripting (Tcl / Python / Perl)

Clock tree, jitter, skew

OCV/AOCV/POCV, MMMC

Independent problem solving

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what's next in electronics and the world.

Job Description

The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tapeout.

Responsibilities

• Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
• Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
• Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
• Drive timing closure through ECO implementation and timing optimization.
• Analyze timing impact due to process, voltage, and temperature variations.
• Support timing signoff for pre-layout and post-layout stages.
• Perform cross-functional reviews for timing convergence and provide recommendations.
• Generate timing reports and communicate closure status to project stakeholders.

Qualifications

• 7-10 years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs.
• Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.
• Hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
• Good understanding of clock tree, clock uncertainty, latency, skew, and jitter.
• Experience in timing constraints development and debugging.
• Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
• Familiarity with timing closure techniques and ECO methodologies.
• Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Good scripting skills in Tcl, Perl, or Python.
• Ability to analyze and resolve timing violations independently.

Nice to have

• Exposure to low-power timing analysis and UPF/CPF-aware STA.
• Familiarity with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure.
• Knowledge of advanced technology nodes and variation-aware signoff methodologies.
• Exposure to automation and flow development.
• Experience in cross-functional collaboration with PD, RTL, and Signoff teams.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.