Staff Engineer - SoC Power Architecture

Qualcomm; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Qualcomm India Private Limited in Bengaluru is seeking an experienced SoC Power Architect to drive power-efficient architectures for next-generation SoCs. The role focuses on optimizing dynamic power, Vmin reduction, leakage power and energy footprint across SOC infra, including CLK tree power and power modelling.

The candidate will perform DVFS and gate-level optimizations, analyze Vmin margins, and drive silicon robustness while developing MATLAB models to quantify PPA KPIs and conducting

Qualifications

• Bachelors or Masters in Electrical/Electronics Engineering or related field.
• 8+ years of experience in SoC Power Architecture, Energy Management & Low-Power Design.
• Strong expertise in Dynamic Power Optimization, Vmin Analysis, Leakage Reduction, and PDN/Power Integrity.

Responsibilities

• Explore and optimize SoC-level power architecture and features across IP blocks.
• Energy and latency study of dynamic power reduction techniques DVFS, clock gating, power gating.
• Analyze Vmin margins and power-performance tradeoffs for silicon robustness.
• Optimize SOC infrastructure power based on use-case profiles and infra utilization.
• Address micro- and macro-idle power optimization techniques across flows.
• Drive leakage reduction and low-power design techniques across advanced nodes.
• Evaluate techniques to manage voltage droops, overshoots, thermal and electrical limits.
• Develop MATLAB models to quantify PPA KPI of power architecture features.
• Use SPICE simulations to back up SOC/System level architecture features.

Skills

Dynamic Power Optimization

Vmin Analysis

Leakage Power Reduction

Low-Power Design Techniques

PDN/Power Integrity Analysis

Power Modeling

SPICE Simulations

PPA KPI Modeling

Education

Bachelors/Masters in Electrical/Electronics Engineering

Tools

MATLAB

SPICE

Job description

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Systems Engineering

General Summary

Seeking an experienced SoC Power Architect to drive power-efficient architectures for next-generation SoCs. The role focuses on optimizing & exploring new features to optimize dynamic power , Vmin reduction, leakage power , use case energy footprint across SOC infra , CLK tree power, power modelling including lab characterization of SOC infra energy impacts & residency profiles of use-cases, data analysis

Key Responsibilities

• Exploring new SoC-level power architecture & optimization features, architecture dependencies with different IP blocks. Driving cross-functional technical evaluations of new features across multiple stakeholders
• Energy & latency sensitivity study of dynamic power reduction techniques DVFS, clock gating, power gating, Micro/Macro power collapse periods
• Analyze and optimize Vmin margins, power-performance tradeoffs, and silicon robustness.
• SOC infrastructure power optimization techniques by studying infra utilization based on use-case profiles ,
• Island use-cases flows, constraints in micro & macro -idle power optimization techniques,
• Drive leakage reduction and low-power design techniques across advanced process nodes.
• Evaluate efficient techniques to manage voltage droops, overshoots, thermal & electrical limits
• Handson experience in developing MATLAB models to quantify PPA KPI of power architecture features
• SPICE simulations to backup SOC/System level architecture features heling optimize Voltage droops, overshoots dynamic load-line management

Required Qualifications

• Bachelor's/Master's degree in Electrical/Electronics Engineering or related field.
• 8+ years of experience in SoC Power Architecture, Energy Management & Low-Power Design.
• Strong expertise in:
• Dynamic Power Optimization
• Vmin Analysis and Margining
• Leakage Power Reduction
• Low-Power Design Techniques
• PDN/Power Integrity Analysis