Engineer II, Physical Design - Cores

SiFive India Private Limited; Bengaluru; On-site; INR 700,000 - 1,300,000; Full time

Job summary

SiFive India Private Limited invites entry-level Physical Design Engineers to grow with our team. You will learn end-to-end ASIC flow from RTL to GDSII, contribute to high-performance CPUs, and collaborate with veterans to understand how architecture impacts power, performance, and area.

Ideal candidates have a strong foundation in computer architecture, digital design, and scripting, with eagerness to learn industry-standard EDA tools and the PD flow across diverse design blocks.

Qualifications

• Solid foundation in computer architecture and digital design.
• Experience with RTL and physical design flow preferred but not required.
• Proficiency in at least one scripting language used in hardware environments.

Responsibilities

• Learn and execute physical design flow including synthesis, placement, and routing.
• Bridge architecture and implementation by understanding RTL.
• Analyze timing, power, and area trade-offs to meet PD targets.
• Develop scripts to automate PD workflows and report parsing.
• Collaborate with RTL, microarchitecture, and methodology teams.

Skills

Verilog/SystemVerilog

Python scripting

VLSI design

Digital logic design

RISC architecture

Education

Bachelors/Masters in EE/CE

Tools

Synopsys

Cadence

Job description

About the Role

At SiFive, we're redefining the compute landscape with our industry-leading RISC-V compute platforms. As a Physical Design Engineer (Entry Level), you will jump-start your career by helping build our next generation of high-performance CPUs. Working closely with industry veterans, you will learn the end-to-end ASIC design flow from RTL to GDSII while contributing to real-world products on advanced process nodes. We are looking for engineers who are passionate about the intersection of computer architecture and physical implementation. Rather than just executing a push-button flow, you will be trained to operate across design-abstraction layers. By leveraging a strong foundational understanding of how CPUs work, you will help bridge the gap between RTL design and physical realities, learning how architectural choices directly impact power, performance, and area (PPA).

Responsibilities

• Learn and Execute: Partner with senior engineers to take CPU blocks through the physical design flow, including synthesis, place & route, and timing closure.
• Bridge Architecture and Implementation: Apply your academic knowledge of computer architecture to understand the underlying RTL.
• Participate in cross-abstraction-layer co-design discussions to see how pipeline stages, datapaths, and control logic translate into physical wires and gates.
• Analyze PPA Trade-offs: Assist in analyzing timing reports, routing congestion, and power metrics to help the team meet aggressive Power, Performance, and Area goals.
• Flow Automation: Write and maintain scripts (Python, Tcl, Bash) to automate physical design workflows, parse reports, and improve team efficiency.
• Collaborate and Grow: Work cross-functionally with RTL, microarchitecture, and methodology teams.

Requirements

• Experience: 3+ years. We are open to considering new graduates with excellent academic credentials. If you have some work experience with physical design implementation it will be a big plus.
• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong Architectural Foundation: A solid academic grasp of computer architecture fundamentals (e.g., RISC instruction sets, processor pipelining, hazards, memory hierarchy, and cache basics).
• Digital Design Knowledge: Strong understanding of digital logic design and the ability to read and understand RTL (Verilog or SystemVerilog).
• VLSI Exposure: Academic coursework, projects, or internship experience related to VLSI design or ASIC flows.
• Scripting Skills: Proficiency in at least one scripting or programming language commonly used in hardware environments (Python, Tcl, Perl, C++, or Bash).
• Growth Mindset: Highly motivated to learn industry-standard EDA tools (Synopsys or Cadence) and eager to understand the 'why' behind physical design challenges, not just the 'how'.

Why join us?

Be part of the RISC-V movement and help define the future of computing architecture.

Work on industry-leading IP adopted by top customers and shipped in high volumes worldwide.

Collaborate with world-class engineers in a supportive, fast-paced, learning environment.

Enjoy a culture that values innovation, ownership, and technical excellence.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in: India Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer.

We celebrate diversity and are committed to creating an inclusive environment for all employees.

Championed by leaders who chose to make a real difference, SiFive led the RISC-V revolution - creating a tremendous wave with the strength to remove economic hurdles and create opportunities for all. Now that we've made history, you have the opportunity to write the future.

If you love to be challenged, you can join the best of the best and get rewarded for doing something that truly matters.