Staff Engineer DFT Engineering

Analog Devices; Gandhinagar; On-site; INR 2,600,000 - 4,200,000; Full time

Job summary

Analog Devices in India seeks a seasoned DFT Engineer to strengthen the VLSI design team. You will design and validate testability features, including LBIST, MBIST, and Boundary Scan, and work with RTL/Netlist and SDF timing. Strong scripting (Perl/Python/Tcl) and Cadence/Siemens DFT tools are essential.

Collaborate with Design/Arch/PT-E/PD groups to implement DFT strategies, perform DFT DRC checks, and drive robust test coverage. Opportunity for mentoring others and impact on high-volume ICs.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronic Engineering.
• 7–10 years of hands-on DFT experience.
• Strong knowledge of LBIST, ATPG, DFT DRC, Scan compression, MBIST.
• Proficiency with Cadence/Siemens DFT tools.
• Scripting in Perl, Tcl, or Python for automation.
• Strong problem solving and teamwork abilities.

Responsibilities

• Collaborate with Design/Arch/PTE/PD teams to ensure testability of ICs.
• Design and implement DFT features such as scan chains and built-in self-test.
• Conduct DFT DRC checks on RTL/Netlist to ensure compliance.
• Utilize Siemens DFT tools to optimize testability metrics.
• Generate ATPG test patterns for SAF and TDF models.
• MBIST design and verification using DFT tools.
• Debug test failures and guide junior DFT engineers.

Skills

LBIST

ATPG

DFT DRC

Scan compression

MBIST

Boundary Scan

Analog DFT

JTAG Architecture

DFT STA Constraint development

Perl/Python/Tcl scripting

Education

Bachelor's/Master's in Electrical/Electronic Engineering

Tools

Cadence DFT tools

Siemens DFT EDA tools

Job description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

Job Description

We are seeking a skilled and experienced DFT Engineer to join our VLSI design team. The ideal candidate should have a strong background in Design for Testability (DFT) techniques, including LBIST (Logic Built-In Self-Test), ATPG (Automatic Test Pattern Generation), DFT DRC (Design Rule Checking), MBIST (Memory Built-in Self-Test), Boundary Scan, JTAG and Analog/Phy DFT.

Responsibilities

• Collaborate with the Design/Arch/PTE/PD team to ensure efficient and effective testability of complex integrated circuits.
• Design and implement DFT features such as scan chains, compression, and built-in self-test structures to enhance testability.
• Conduct DFT DRC checks in RTL/Netlist database to ensure compliance with DFT guidelines and rules.
• Utilize Siemen’s DFT tool to perform DFT analysis and optimize testability metrics.
• Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models using on-chip test compression techniques.
• MBIST Design (including repair) and Verification using Siemen’s EDA tool.
• Validation of DFT structures/patterns in RTL, Netlist with and without SDF.
• Work closely with the verification team to define and implement DFT verification plans.
• Work closely with physical design team for DFT implementation/constraints strategy for synthesis/STA.
• Analyze and debug test failures and collaborate with the test engineering team to resolve issues.
• Provide guidance and mentorship to junior DFT engineers.

Qualifications

• Bachelor's/Master's degree in Electrical/Electronic Engineering, or a related field.
• 7-10 years of hands-on experience in DFT methodologies and techniques.
• Strong knowledge of LBIST, ATPG, DFT DRC, Scan compression, Low power DFT Techniques, MBIST, Boundary Scan, Analog DFT, JTAG Architecture, DFT STA Constraint development.
• Hand-on experience/expertise in Cadence/Siemen’s DFT EDA tools for Scan stitching, DRC, ATPG, Coverage improvement, MBIST, Boundary Scan.
• Proficiency in scripting languages such as Perl, Tcl, and/or Python for automation.
• Solid understanding of digital design fundamentals, RTL coding, Lint/CDC, Low Power Checks and ASIC design flow.
• Excellent problem-solving skills and ability to work effectively in a team-oriented environment.
• Strong communication and interpersonal skills.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days