Senior DD Engineer

Analog Devices; Bengaluru; On-site; INR 3,000,000 - 5,000,000; Full time

Job summary

Analog Devices, Inc. in Bengaluru seeks an experienced Senior DFT Engineer to define and optimize DFT architecture for SOCs.

You will collaborate with Product/Test engineering to reduce test cost while ensuring high coverage, implement SCAN/MBIST techniques, and guide validation across pre- and post-silicon stages. You should have 4–8 years in DFT, hands-on post-silicon work, and experience with Tessent DFT suites; strong scripting and HDL skills are essential to drive test flows across global

Qualifications

• 4-8 years of industry experience in the DFT domain.
• Must have experience bringing at least one or two products to production from architecture phase, scan implementation and simulations.
• Hands-on experience in post-silicon activities.
• Exposure to Tessent DFT (SCAN, MBIST, LBIST, OCC, EDT, SSN, Boundary Scan) preferred.
• Exceptional interpersonal and communication skills for working with global CAD teams.
• Scripting skills in Perl/Python/TCL and good command over HDLs.

Responsibilities

• Define and optimize DFT architecture for high-performance testability.
• Work with lead Product/Test engineering during DFT definition to reduce test cost and improve coverage.
• Develop / upgrade SCAN & MBIST insertion flows and timing constraints.
• Implement ATPG flows for various fault models and test patterns.
• Support post-silicon bring-up with ATE patterns and failure analysis.
• Improve DFT methodology in line with industry best practices.

Skills

DFT

SCAN

MBIST

LBIST

OCC

EDT

Python/Perl/TCL scripting

HDL proficiency

Cadence tools

Physical design timing

Export controls knowledge

Tools

Cadence Genus

Tempus

Tessent DFT

Job description

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X .

Senior DFT Engineer Responsibilities

DFT architecture definition Understand SoC architecture and test requirements.

Work very closely with the lead Product/Test engineering throughout the DFT definition phase to determine efficient ways to optimize test cost and achieve high test coverage.

Drive and optimize DFT architecture for high performance and efficiency: SCAN - scan partition, compression, at-speed, IR and low power

MBIST for memories

JTAG boundary scan insertion

Handle responsibilities pertaining to both block and top-level activities in Hierarchical Scan.

Implementation

Develop / Upgrade SCAN & MBIST Insertion flows

Develop appropriate timing constraints for SCAN/MBIST modes and debug timing violations

ATPG flow implementation catering to various fault models, test pattern generation

SCAN , MBIST & BSCAN Pattern Simulation

Solutions to test analog macros

Post-Silicon bring-up/support

Work with Evaluation/Test Engineering team to bring-up patterns on ATE

Work on failure analysis as required

Work with the Operation team on test cost and yield improvement

Improve DFT methodology to be in sync with latest best practices and technology in the industry

Work closely with physical design team throughout the development cycle.

Should be able to guide newly inducted team members on their bring-up on flow, methodology and execution methods in all aspects of DFT.

Requirements

4-8 years of industry experience in DFT domain.

Must have experience in bringing atleast one or two products to successful production from architecture phase, scan implementation and simulations.

Must have hands-on experience working on post-silicon activities.

Having working experience with tessent DFT (SCAN, Mbist, Lbist, OCC, EDT, SSN, Boundary Scan) will be preferred.

Exceptional interpersonal and communication skills are critical for working, influencing and collaborating with product development groups and CAD tool teams spread across the globe.

Scripting skills in Perl/Python/TCL and a good command over HDLs.

Candidates with exposure to deep submicron effects and low power implementation using UPF/CPF will be at an advantage. Candidates with experience using Cadence digital implementation tools (Genus, Tempus) would be preferred.

Prior experience of timing closure/physical design will be an added plus.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced

Required Travel: Yes, 10% of the time

Shift Type: 1st Shift/Days