Staff Application Engineer ECO Timing

Synopsys Inc; Hyderabad; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Synopsys is seeking an experienced timing and design-closure expert to work with customers in Hyderabad. You will diagnose complex timing issues on live silicon, collaborate with R&D to shape features, and drive best practices for advanced-node signoff.

The role requires 6–8 years in semiconductor design, strong TCL/Perl scripting, and deep understanding of P&R/STA/ECO flows. You will engage with customer teams and provide hands-on guidance through tapeout.

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering or equivalent.
• 6–8 years of hands-on semiconductor design with P&R, STA, extraction, and ECO flows.
• Deep expertise in timing, physical constraints, parasitic annotation, and timing analysis.
• Experience on 7nm/5nm/3nm nodes preferred.
• Strong scripting in TCL and Perl to automate tasks.
• Solid understanding of ASIC flow, VLSI fundamentals, and CAD principles.

Responsibilities

• Diagnose and resolve timing, extraction, and design closure issues on live silicon.
• Collaborate with R&D to shape product roadmaps and specifications.
• Deploy best practices for timing signoff and PPA on advanced nodes.
• Provide technical training and demos on STA, ECO, and design methods.
• Support project execution from early design through tapeout with guidance.
• Script automation to streamline customer workflows and reduce turnaround time.

Skills

Timing signoff

Design closure

Customer interaction

TCL scripting

Perl scripting

Automation workflows

Cross-functional collaboration

Education

BS in Electrical Engineering or Computer Engineering

MS in Electrical Engineering or Computer Engineering

Tools

Place & Route (P&R)

Static Timing Analysis

Parasitic extraction

TCL scripting

Perl scripting

CAD/EDA tools

Job description

Job Description:

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in the trenches of timing signoff and design closure, and you know the difference between a chip that tapes out on schedule and one that misses by three months because someone ignored a critical timing path in the second pass. You are the engineer who gets called when a customer's design is stuck at 95% timing closure and no one can figure out why. You do not just run tools, you understand what the tools are actually doing under the hood, and you know when to trust the results and when to dig deeper. Working across P&R, STA, and ECO flows is second nature to you. You have debugged parasitic extraction issues at 3nm, optimized PPA targets on real silicon projects, and written enough TCL and Perl scripts to automate workflows that used to take days. You are comfortable sitting with a customer's design team in Hyderabad one day and presenting technical tradeoffs to their management the next, translating between "this violates setup by 200ps" and "this impacts your product schedule by two weeks." You do not wait for perfect data. You work with what you have, ask the right questions, and move. At Synopsys, you will work with customers who are pushing the limits of semiconductor design, and what you enable will directly affect whether their chips work.

What You'll Be Doing

• Work directly with customers and partners to diagnose and resolve complex timing, extraction, and design closure issues on live silicon projects using Synopsys STA, ECO, and P&R tools


• Collaborate with R&D teams to shape product roadmaps, validate new features, and translate real-world customer pain points into actionable technical specifications


• Deploy best practices for timing signoff, parasitic annotation, and physical design methodologies to help customers hit aggressive PPA targets on advanced nodes


• Deliver technical training and product demos to customer engineering teams and Synopsys field staff, covering STA flows, ECO strategies, and design implementation techniques


• Support customer project execution from early design phases through tapeout, providing hands‑on guidance on constraint setup, timing closure, and multi-die design challenges


• Partner with Sales and customer technical managers to identify design bottlenecks, scope technical solutions, and communicate product value at both engineering and executive levels


• Script automation solutions in TCL, Perl, and other languages to streamline customer workflows and reduce turnaround time on critical design tasks

The Impact You Will Have

• Enable customers to achieve faster design closure and meet tapeout schedules on complex, multi-die designs at 5nm and below


• Reduce customer project turnaround times by introducing engineering techniques and automation that eliminate manual bottlenecks


• Influence the development roadmap of Synopsys timing and ECO products by providing R&D with actionable feedback from real customer engagements


• Build Synopsys' reputation as the trusted partner for timing signoff and design closure across the semiconductor industry in India and beyond


• Empower customer teams and internal field engineers through knowledge transfer, training, and technical mentorship that raises the bar for design execution


• Accelerate adoption of new Synopsys product releases by being the technical bridge between early access programs and production customer deployments


• Help customers optimize Power, Performance, and Area outcomes that directly affect the competitiveness and success of their silicon products

What You'll Need

• BS or MS in Electrical Engineering, Computer Engineering, or equivalent technical discipline


• 6-8 years of hands‑on experience in semiconductor design, with direct work in Place & Route, Static Timing Analysis, extraction, and Engineering Change Order flows


• Deep technical expertise with timing and physical constraint methodologies, parasitic annotation, and timing analysis for complex IC designs


• Proven experience executing silicon chip projects through physical design and timing closure, especially on advanced technology nodes like 7nm, 5nm, or 3nm


• Strong scripting skills in TCL and Perl, with the ability to automate design tasks and build custom flows


• Solid understanding of ASIC design flow, VLSI fundamentals, and CAD engineering principles across the full design cycle


• Experience working directly with customers or cross‑functional teams in a technical support, applications engineering, or field engineering capacity is a strong plus

Who You Are

• You can walk into a room with a customer's design team, understand their timing violations in the first 20 minutes, and outline a closure plan before you leave


• You explain complex technical tradeoffs clearly to both engineers and management, without losing the nuance or oversimplifying the problem


• You are proactive about solving problems, you do not wait to be told what to do when a customer design is stuck, you dig in and figure it out


• You stay organized and focused when managing multiple customer engagements, product validation tasks, and internal collaboration threads at the same time


• You are genuinely curious about new technologies and design methodologies, and you actively seek out ways to improve your skills and expand your technical toolkit


• You thrive on collaboration and knowledge sharing, whether that is training a customer team on best practices or working with R&D to refine a product feature

The Team You'll Be Part Of

You will join the ECO Field team at Synopsys in Hyderabad, a highly skilled group focused on enabling customer success in timing signoff and design closure. The team partners with R&D, Sales, and technical managers to deliver industry-leading solutions, drive new product adoption, and address complex technical challenges. Together, you will foster a culture of technical excellence, build deep expertise, and help customers achieve their design goals faster and more efficiently.