Field Application Engineer, Verification

Synopsys, Inc.; Bengaluru; On-site; INR 1,800,000 - 2,600,000; Full time

Job summary

Synopsys, Inc. is seeking a Field/Application Engineer focused on RTL verification to collaborate with semiconductor design teams in India. You will deploy VC SpyGlass, VCS, and related tools, debug complex RTL signoff issues, and drive flow improvements with R&D and product validation teams.

You will lead customer engagements across time zones, ensuring milestones are met and tapeouts stay on schedule. Strong problem-solving and communication skills are essential.

Qualifications

• Hands-on RTL verification experience with ASIC flows.
• Experience across RTL-to-tapeout verification processes.
• Comfort with customer engagements and problem solving.

Responsibilities

• Deploy and optimize Synopsys verification solutions at customers.
• Debug RTL signoff issues and reduce tapeout blockers.
• Lead technical engagements onsite or remote.
• Translate customer feedback into flow improvements.
• Train customer teams on methodologies and best practices.

Skills

RTL verification

VHDL/Verilog/SystemVerilog

CDC and RDC

UPF/CPF low power

Formal verification basics

Customer-facing communication

Education

BE/BTech in Electronics or CS

3-5 years of experience in ASIC design or verification

Tools

VC SpyGlass

VCS

VC LP

VC Formal

Verdi

Job description

Alternate Job Titles

• Field Application Engineer, Verification
• Senior Applications Engineer, RTL Signoff
• Customer Success Engineer, Verification Solutions
• Technical Application Engineer, Design Verification
• Solutions Engineer, Verification and Low Power

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years deep in RTL verification flows and you have learned that the hardest problems are rarely the ones in the datasheet. They show up three weeks before tapeout when a CDC violation surfaces in a corner case no one thought to model, or when a low power domain interaction breaks in ways the testbench never caught. You live for those moments because solving them well is what keeps chips from respinning.

You are equally comfortable reading SystemVerilog assertions, walking a customer through a SpyGlass run, and sitting with an R&D team to explain why a methodology needs to flex for a real design. You do not wait for someone to hand you a script. You write it, test it, and then show the customer how to own it themselves.

Working across time zones does not faze you. Neither does jumping into a customer war room when a project is stuck. You know that adoption is not about features, it is about trust, and trust comes from showing up, understanding the problem, and delivering something that actually moves the schedule forward. At Synopsys, you will work with semiconductor teams building the chips that power everything, and what you enable will matter.

What You'll Be Doing

• Work directly with semiconductor design teams across the region to deploy and optimize Synopsys verification solutions including VC SpyGlass, VCS, VC LP, VC Formal, and Verdi
• Debug complex RTL signoff issues in customer designs, CDC violations, lint errors, RDC problems, low power UPF conflicts, and formal property failures, and turn those into repeatable methodology improvements
• Partner with Synopsys R&D and product validation teams to develop new flows, reproduce customer issues, and drive tool enhancements that solve real tapeout blockers
• Lead technical engagements during critical project phases, onsite or remote, ensuring customers hit their verification milestones and tapeout schedules
• Gather requirements from customer feedback and design challenges, translate them into flow improvements, and work with product teams to prioritize and track delivery
• Coordinate with account managers and technical account managers to shape customer strategies, drive tool adoption, and support business growth across your accounts
• Train customer engineering teams on verification methodologies, tool usage, and best practices that reduce verification cycle time and improve signoff quality

The Impact You Will Have

• Enable customers to close CDC, lint, and low power signoff weeks or months faster by deploying the right methodology at the right time in their flow
• Reduce customer respins by catching critical RTL issues early, before they reach gate-level or silicon
• Drive adoption of Synopsys verification tools across new projects and teams, expanding footprint and deepening technical relationships with key accounts
• Influence Synopsys product roadmaps by surfacing real customer pain points and working with R&D to deliver features that matter
• Build repeatable flows and reference methodologies that scale across multiple customer projects and design teams
• Strengthen customer confidence in Synopsys solutions by being the engineer they call when something breaks and needs to get fixed now
• Contribute to the success of chips powering AI, automotive, mobile, and cloud infrastructure by ensuring verification does not become the bottleneck

What You'll Need

• BE/BTech/ME/MTech in Electronics Engineering, Computer Science, or Microelectronics with 3-5 years of hands-on industry experience in ASIC design or verification
• Strong command of VHDL, Verilog, and SystemVerilog RTL, and a solid understanding of ASIC design and verification flows from RTL to tapeout
• Proven experience with RTL signoff flows including linting, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and property checking using static and formal verification tools
• Hands-on work with low power verification techniques using UPF or CPF, and experience debugging power intent issues in real designs
• Exposure to simulation and verification methodologies including directed tests, constrained random testing, assertions, coverage-driven verification, and gate-level simulation (GLS)
• Working knowledge of Synopsys EDA tools such as VC SpyGlass, VCS, VC LP, VC Formal, FishTail, or Verdi is a strong plus
• Comfort working in ambiguity, you can take a vague customer problem, ask the right questions, and turn it into a clear technical plan

Who You Are

• You can walk into a customer meeting, listen to a verification challenge, and sketch out a solution approach on the whiteboard that the team actually believes in
• You are the kind of engineer who does not just report a tool issue, you create a minimal reproducible test case, propose a workaround, and follow up until it is resolved
• Working across global teams and time zones does not slow you down, you coordinate effectively, keep stakeholders aligned, and do not let details fall through the cracks
• You know how to explain a complex CDC violation or formal proof failure to a design lead in a way that makes sense without oversimplifying the technical reality
• You build relationships by being reliable, when you say you will deliver a flow or a debug session, it happens
• You are curious about what is coming next in chip design, AI workloads, automotive safety, advanced nodes, and you want to be part of enabling it

The Team You'll Be Part Of

You will join the Customer Success Group, a global team that partners directly with semiconductor companies to solve high-value verification and design problems. The team works closely with R&D, product validation, account management, and technical account managers to drive adoption of Synopsys solutions and ensure customer projects succeed through tapeout. You will be part of a regional applications engineering team supporting customers across India, collaborating with engineers worldwide, and contributing to methodologies that scale across the business.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.