STA Lead

AMD; Bengaluru Urban; On-site; INR 6,000,000 - 9,000,000; Full time

Job summary

AMD in Bengaluru seeks an experienced Full Chip SoC Timing Lead to drive timing closure across complex SoCs, signoff, and tapeout for advanced nodes. You will own constraints, STA, ECOs, and cross-functional collaboration with RTL, PD, CTS, DFT, and power teams.

The role requires 15+ years in ASIC/SoC timing analysis, strong leadership, and deep expertise in timing budgets and signoff. A hands-on expert in advanced technology nodes is essential for this senior position.

Qualifications

• Experience leading full-chip timing activities from synthesis through signoff and tapeout.
• Expertise in STA, timing constraints, MMMC flows, and cross-functional collaboration.

Responsibilities

• Lead full-chip timing closure for complex SoC/ASIC designs across modes and corners.
• Own and drive timing signoff from synthesis to final tapeout.
• Develop, validate, and maintain timing constraints including SDC for full-chip and block-level integration.
• Perform and review static timing analysis (STA) for setup, hold, recovery, removal, clock gating, and async paths.
• Drive MMMC timing methodology and ensure robust timing convergence across PVT corners.
• Collaborate with physical design teams on floorplanning, placement, CTS, routing, and post-route timing optimization.
• Analyze and resolve timing violations related to datapath, clock path, cross-talk, noise, derates, and variation effects.
• Lead timing ECO strategies and execute closure with minimal impact to power, area, and performance.
• Coordinate with RTL/design teams to identify architectural or logic changes for timing improvement.
• Coordinate with IP/block owners for timing budgeting, interface timing closure, and hierarchical timing signoff.
• Ensure signoff quality using industry-standard tools and methodologies.
• Drive correlation between implementation timing and signoff timing.
• Lead tapeout readiness reviews and provide timing risk assessment to program leadership.
• Mentor junior engineers and define best practices for timing methodology and closure.

Skills

Full-chip timing closure

STA & timing signoff

Timing constraints (SDC)

MMMC timing

SI/crosstalk analysis

ECO closure

RTL/PD/DFT coordination

Floorplanning & placement

Clocking architecture

Timing debugging & closure

Education

Bachelor's or Master's degree in Electronics / Electrical Engineering / VLSI / Microelectronics / Computer Engineering

Tools

Synthesis tools

Place-and-route tools

Timing analysis tools

Signoff tools

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

PMTS SILICON DESIGN ENGINEER

THE ROLE:

We are seeking an experiencedFull Chip SoC Timing Leadwith15+ years of industry experienceinASIC/SoC design implementation and timing closure. The ideal candidate will lead full-chip timing activities from synthesis through place-and-route, signoff, and tapeout for complex SoCs in advanced technology nodes. This role requires deep expertise inSTA, timing constraints, MMMC flows, SI/crosstalk analysis, ECO closure, and cross-functional collaborationwith RTL, PD, CTS, DFT, power, and signoff teams.

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Leadfull-chip timing closurefor complex SoC/ASIC designs across all modes and corners.
• Own and drivetiming signofffrom synthesis to final tapeout.
• Develop, validate, and maintaintiming constraintsincluding SDC for full-chip and block-level integration.
• Perform and reviewstatic timing analysis (STA)for setup, hold, recovery, removal, clock gating, and async paths.
• DriveMMMC timing methodologyand ensure robust timing convergence across PVT corners.
• Work closely withphysical design teamson floorplanning, placement, CTS, routing, and post-route timing optimization.
• Analyze and resolvetiming violationsrelated to datapath, clock path, cross-talk, noise, OCV/AOCV/POCV, derates, and variation effects.
• Leadtiming ECO strategiesand execute closure with minimal impact to power, area, and performance.
• Collaborate withRTL/design teamsto identify architectural or logic changes required for timing improvement.
• Coordinate withIP/block ownersfor timing budgeting, interface timing closure, and hierarchical timing signoff.
• Ensure signoff quality using industry-standard tools and methodologies.
• Drive correlation betweenimplementation timingandsignoff timing.
• Lead tapeout readiness reviews and provide timing risk assessment to program leadership.
• Mentor junior engineers and define best practices for timing methodology and closure.

PREFERRED EXPERIENCE:

• • Bachelor's or Master's degree inElectronics / Electrical Engineering / VLSI / Microelectronics / Computer Engineering.
  • 15+ yearsof hands-on experience inASIC/SoC timing analysis and timing closure.
  • Strong expertise infull-chip STA and timing signofffor large-scale SoCs.
  • Proven experience inadvanced technology nodes(such as7nm, 5nm, 3nmor similar).
  • Strong knowledge ofsynthesis, place-and-route, extraction, and signoff flows.
  • Experience withtiming budgeting and hierarchical/full-chip integration.
  • Solid understanding ofclocking architecture, CDC implications, and timing exception handling.
  • Ability to debug complex timing issues and drive closure under aggressive schedule targets.
  • Strong communication, stakeholder management, and leadership skills.

#LI-AB1

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.