Sr Staff High-Speed Interface Verification Engineer

Synopsys, Inc.; Kondapur; On-site; INR 4,200,000 - 6,400,000; Full time

Job summary

Synopsys, Inc. seeks an experienced verification engineer for high-speed SerDes IP at the mixed-signal interface. You will lead UVM-based verification, define test plans for PCIe, Ethernet, USB3.1, and drive debug across digital and analog domains to ensure silicon readiness.

You will build advanced UVM testbenches, collaborate with design teams, and mentor others while managing customer escalations and contributing to pre-/post-sales discussions.

Qualifications

• 7+ years of hands-on verification in ASIC or mixed-signal environments.
• Deep expertise in UVM and SystemVerilog.
• Experience with digital/analog co-simulation tools.
• Knowledge of PCIE, Ethernet, or USB3.1 protocols.
• Understanding full ASIC development flow from architecture to bring-up.
• Experience writing complex system-level testbenches in UVM.
• Debug waveform-level failures in digital and analog domains.

Responsibilities

• Lead verification of high-speed SerDes IP using UVM and SystemVerilog testbenches in mixed-signal co-simulation environments
• Define, track, and execute verification test plans for PCIE, Ethernet, USB3.1, and other high-speed protocols from architecture through tapeout
• Debug simulation failures across digital and analog domains, working directly with waveform viewers, mixed-signal simulators, and protocol analyzers
• Build and extend UVM testbenches with constrained random sequences, coverage models, and checkers that target real-world corner cases
• Collaborate daily with digital, analog, and mixed-signal design teams to align verification strategy with design intent and silicon bring-up realities
• Manage customer escalations by reproducing issues, root-causing failures, and driving resolution with engineering and field teams
• Drive pre-sales and post-sales technical discussions with customers, translating verification results into confidence and clarity

Skills

UVM

SystemVerilog

Constrained random

Functional coverage

Assertions

Analog/digital co-simulation

Debugging

Education

MTech or BTech in Electronics

Tools

AMS simulators

Mixed-signal simulators

SystemVerilog simulators

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of mixed-signal verification, and you know that the hardest problems live at the boundary where digital meets analog. You are the engineer who can read a waveform, spot the timing violation that three others missed, and trace it back to a testbench assumption made two months ago. You do not just run regressions, you architect verification strategies that catch the subtle, the corner case, the thing that only shows up at 56 Gbps under specific PVT conditions.

What You'll Be Doing

• Lead verification of high-speed SerDes IP using UVM and SystemVerilog testbenches in mixed-signal co-simulation environments
• Define, track, and execute verification test plans for PCIE, Ethernet, USB3.1, and other high-speed protocols from architecture through tapeout
• Debug simulation failures across digital and analog domains, working directly with waveform viewers, mixed-signal simulators, and protocol analyzers
• Build and extend UVM testbenches with constrained random sequences, coverage models, and checkers that target real-world corner cases
• Collaborate daily with digital, analog, and mixed-signal design teams to align verification strategy with design intent and silicon bring-up realities
• Manage customer escalations by reproducing issues, root-causing failures, and driving resolution with engineering and field teams
• Drive pre-sales and post-sales technical discussions with customers, translating verification results into confidence and clarity

The Impact You Will Have

• Ensure that SerDes IP shipping to customers meets performance, functionality, and reliability targets before it ever reaches silicon
• Reduce post-silicon debug cycles by catching mixed-signal integration issues early through rigorous co-simulation and coverage-driven verification
• Set the technical direction for verification methodology across current and next-generation SerDes products
• Accelerate customer adoption and satisfaction by resolving escalations quickly and providing clear, actionable technical guidance
• Mentor and elevate the verification team by establishing best practices, code reviews, and a culture of ownership and quality
• Contribute directly to Synopsys IP competitiveness by delivering verification environments that scale across protocol variants and process nodes
• Influence product roadmaps by surfacing verification insights that shape architecture and design decisions upstream

What You'll Need

• MTech or BTech in Electronics, Electrical Engineering, Computer Science, or equivalent with 7+ years of hands‑on verification experience in ASIC or mixed‑signal environments
• Deep expertise in UVM, SystemVerilog, and verification methodologies including constrained random testing, functional coverage, and assertions
• Proven experience with digital/analog co‑simulation tools and methodologies, including AMS simulators and mixed‑signal verification flows
• Working knowledge of high‑speed interface protocols such as PCIE, Ethernet, or USB3.1, including protocol‑level verification and compliance
• Strong understanding of the full ASIC development flow from architecture specification through RTL design, verification, and hardware bring‑up
• Experience writing complex system‑level testbenches in UVM, including sequence libraries, scoreboards, and protocol monitors
• Hands‑on experience debugging waveform‑level failures in both digital logic and analog circuit behavior

Who You Are

• You can walk into a room with analog designers discussing CDR loop dynamics and digital engineers debating clock domain crossings, and contribute meaningfully to both conversations
• You have managed customer escalations before and know how to balance urgency with thoroughness, reproducing the issue, isolating root cause, and communicating status without overselling or underselling
• You lead by setting the example, whether that is writing cleaner testbench code, asking the hard question in a design review, or staying late to close a critical bug before tapeout
• You make decisions with incomplete information, prioritize what matters, and course‑correct when new data arrives without losing momentum
• You can explain a complex verification failure to a field applications engineer in two sentences and to a design lead in a ten-minute whiteboard session, adjusting depth and framing to the audience
• You build relationships across functions because you know that the best verification strategies come from understanding what design, applications, and customers actually need

The Team You'll Be Part Of

You will be part of a highly skilled team of digital, analog, and mixed‑signal engineers responsible for delivering high‑end mixed‑signal designs from specification to implementation. This team thrives on collaboration, excellence, and pushing the boundaries of technology to deliver top‑n SerDes products to customers worldwide.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings.