Sr Staff Engineer, Physical Design

Synopsys Inc; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Synopsys Inc in Bengaluru, India is seeking a Sr Staff - Physical Implementation Flow (8+ years) to drive next-gen physical design flows, manage timing closure and signoff, and contribute to PCI/CXL/IDE Controller IPs.

You will collaborate with global teams, perform synthesis, floorplanning, PnR, STA, and power integrity, while maturing guides for customers and internal teams. Strong scripting and communication skills are essential.

Qualifications

• Extensive experience with ASIC design flow and hierarchical physical design strategies.
• Strong background in timing analysis, constraints management, and frontend synthesis.
• Experience with physical-aware synthesis, formality, and various verification strategies.
• Knowledge of PrimePower-based power analysis and clock gating for power reduction.
• Good knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools.

Responsibilities

• Work on new processes for physical implementation flows and cutting-edge technology nodes.
• Collaborate with functional teams to optimize and develop Next Gen PCI/CXL/IDE Controller IPs.
• Defining signoff criteria with a strong focus on Timing Closure.
• Maturing the physical implementation guide used for customers and internal hardening teams.
• Participating in next-generation physical design methodology and flow development.
• Performing physical design implementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signoff.
• Evaluating PPA targets (Area/Speed/Power) and collaborating with the design team to improve design and constraints.

Skills

ASIC design flow

Timing analysis

Signoff criteria

Scripting skills

Communication skills

Team collaboration

Tools

PrimePower

Synopsys tools

Job description

Sr Staff - Physical Implementation Flow (experience - 8+ Years)

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for physical implementation flows and cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop Next Gen PCI/CXL/IDE Controller IPs. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-based power analysis. Your scripting skills are excellent, and you are innovative, self-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria.

What You'll Be Doing:

• Working on new processes for physical implementation flows and cutting-edge technology nodes.
• Collaborating with functional teams to optimize and develop Next Gen PCI/CXL/IDE Controller IPs.
• Defining signoff criteria with a strong focus on Timing Closure.
• Maturing the physical implementation guide used for customers and internal hardening teams.
• Participating in next-generation physical design methodology and flow development.
• Performing physical design implementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff.
• Evaluating PPA targets (Area/Speed/Power) and collaborating with the design team to improve design and constraints.

The Impact You Will Have:

• Driving the development of next-generation physical design methodologies and flows.
• Ensuring the optimization and successful implementation of cutting-edge technology nodes.
• Contributing to the development of high-performance silicon chips and software content.
• Enhancing the efficiency and performance of Synopsys' IPs through rigorous timing closure and signoff criteria.
• Improving customer satisfaction by maturing physical implementation guides.
• Supporting the achievement of Synopsys' operational goals through innovative design solutions.

What You'll Need:

• Extensive experience with ASIC design flow and hierarchical physical design strategies.
• Strong background in timing analysis, constraints management, and frontend synthesis.
• Experience with physical-aware synthesis, formality, and various verification strategies.
• Knowledge of Primepower-based power analysis and clock gating for power reduction.
• Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools.
• Strong physical implementation flow debugging skills and scripting abilities.

Who You Are:

Innovative, self-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solving abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design.

The Team You'll Be A Part Of:

You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performance solutions that meet the evolving needs of our customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.