ASIC Digital Design Staff Engineer

Synopsys Inc; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Health and wellness benefits

Financial benefits

Job summary

Synopsys Inc. seeks an experienced verification lead to own Subsystem verification and drive strategy across DDR, HBM, PCIe, and related IPs. You will build cohesive UVM environments and collaborate with RTL designers to ensure correctness across silicon blocks.

You will mentor engineers, define test plans, and push closure on coverage and regression. This role is critical to delivering high‑quality SoCs powering AI, automotive, and cloud workloads.

Qualifications

• Bachelor’s or Master’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field.
• 8+ years of hands-on ASIC/FPGA verification with ownership from planning through signoff.
• Strong SystemVerilog and UVM testbench development, including assertions and constrained random stimulus.
• Proven ability to define verification strategies, write test plans, and drive coverage closure.
• Experience leading a verification team and collaborating across design, architecture, and verification.

Responsibilities

• Lead verification ownership for critical Subsystem areas, driving strategy and execution with a team on DDR, HBM, PCIe, UCIe, Ethernet, UALink or UFS IP.
• Define, implement, and track detailed verification test plans mapping coverage goals to silicon risk.
• Build and maintain Subsystem-level UVM testbenches, integrating RTL and behavioral models.
• Write complex test cases, assertions, and checkers; debug simulation failures to root cause.
• Extract and drive closure on functional and code coverage metrics; close gaps before signoff.
• Manage regression suites and contribute to ongoing improvement of verification flows and automation.

Skills

SystemVerilog

UVM

Testbench development

Mentoring/leadership

Coverage analysis

Education

Bachelor's or Master's in Electronics / Electrical / Computer Engineering

Tools

Assertions

Constrained random stimulus

Debugging tools

Regression tooling

Job description

Job Description:

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are an engineer who gets energized when you see a complex Subsystem come together and actually work, not just pass a basic smoke test, actually work under corner cases that would make most people walk away. You have spent enough time in verification to know that the difference between a clean tapeout and a costly respin often lives in a test case no one thought to write or a coverage hole no one noticed until it was too late. That keeps you up at night in the best way.

You think in test plans, not checklists. When someone hands you a spec for a DDR or PCIe or UCIe interface, you are already mapping out where the edge cases hide and what kind of stimulus will actually stress the design. Debugging a waveform with thousands of signals does not intimidate you, it is where you do your best work. You ask the right questions early, whether that is clarifying an ambiguous requirement with an architect or pushing back on an RTL designer when something does not smell right.

Leading a team does not mean having all the answers. It means knowing when to dive deep yourself and when to unblock someone else. You have mentored engineers before, or you are ready to, and you understand that the best verification environments are built by people who share what they learn. At Synopsys, you will work on Subsystems that power the chips behind AI, automotive, and cloud infrastructure, and the verification rigor you bring will directly determine whether those chips work.

What You'll Be Doing

• Lead verification ownership for critical Subsystem areas, driving strategy and execution alongside a team of verification engineers working on DDR, HBM, PCIe, UCIe, Ethernet, UALink, or UFS IP integration
• Define, implement, and track detailed verification test plans that map coverage goals to real silicon risk, ensuring nothing slips through
• Build and maintain Subsystem-level UVM testbenches in SystemVerilog, integrating RTL and behavioral models into a cohesive verification environment
• Write complex test cases, assertions, and checkers that catch the corner cases other teams miss, and debug simulation failures down to root cause
• Extract, analyze, and drive closure on functional coverage and code coverage metrics, working with the team to close gaps before signoff
• Manage regression suites and contribute to continuous improvement of verification flows, methodologies, and automation
• Collaborate directly with RTL designers and architects across global sites to ensure functional correctness and alignment on design intent

The Impact You Will Have

• Enable successful verification and deployment of high-performance Subsystems that ship in leading-edge SoCs powering AI, automotive, cloud, and mobile applications worldwide
• Catch critical design issues early in the verification cycle, reducing time-to-market and avoiding costly silicon respins that can delay product launches by months
• Advance verification methodologies and AI-assisted verification flows that influence how Synopsys and the broader industry approach Subsystem-level verification
• Build verification environments and test strategies that become reusable assets across multiple product generations and IP families
• Mentor and grow verification engineers on your team, raising the technical bar and building a culture of rigor and knowledge sharing
• Strengthen Synopsys' reputation as the premier provider of high-speed connectivity IP Subsystems through engineering excellence that customers depend on
• Set industry standards for IP verification quality and methodology, contributing to Synopsys' leadership in chip design and EDA

What You'll Need

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related technical field
• 8+ years of hands‑on experience in ASIC or FPGA verification, with a track record of owning verification deliverables from planning through signoff
• Proven expertise developing SystemVerilog and UVM-based testbenches for complex ASIC designs, including experience with assertions, checkers, and constrained random stimulus
• Strong ability to define verification strategies, write rigorous test plans, and drive coverage closure using functional coverage and code coverage analysis
• Experience technically leading a verification team or mentoring engineers, with demonstrated success collaborating across design, architecture, and verification teams
• Deep understanding of verification metrics, regression management, and debugging complex simulation failures in large-scale environments
• Experience with high-speed interface protocols such as DDR, HBM, PCIe, UCIe, Ethernet, UALink, or UFS is highly desirable and will set you apart

Who You Are

• You can look at a failing regression, pull up the waveform, and within an hour tell the team whether it is a testbench bug, an RTL issue, or a timing corner no one considered
• When a junior engineer brings you a stuck debug, you do not just give them the answer, you walk them through how to isolate the problem so they can solve the next one themselves
• You push back when a test plan is too shallow or a coverage model misses an important state transition, and you do it in a way that makes the team stronger, not defensive
• You stay current on verification techniques and tools, whether that is exploring AI-assisted verification flows or adopting new UVM patterns that improve reuse and debug speed
• You communicate clearly across time zones and disciplines, translating verification status into terms that architects, designers, and project leads can act on
• You take ownership seriously, if a coverage hole or test gap exists in your area, you do not wait for someone else to notice, you flag it and drive it to closure

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings.