Sr Manager, Post-Silicon Validation Engineering

Lattice Semiconductor (india); Pune District; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

Lattice Semiconductor (india) is seeking a Senior Manager in Silicon Design Validation to lead a skilled team responsible for ensuring the quality and performance of advanced semiconductor products across the post-silicon lifecycle.

You will set validation strategies, oversee bench hardware/software needs, develop RTL test logic, drive silicon bring-up, and collaborate with design, verification, manufacturing, test, quality, and marketing.

Qualifications

• 15+ years of silicon validation experience including leadership.
• Master's or Bachelor's in Electrical Engineering.
• Proven track record managing complex validation projects and leading cross-functional teams.
• Deep expertise in high-speed SerDes interface characterization and protocol testing (PCIe, Ethernet, SDI, CoaXpress, JESD204, MIPI D-PHY, CSI/DSI-2, USB, DisplayPort, HDMI).
• Strong background in high-speed board design, signal integrity evaluation and debug.
• Proficient in Verilog/VHDL and FPGA design tools.
• Skilled in test automation development using Python and Perl.
• Solid understanding of statistical analysis and tools such as JMP and R.
• Hands-on experience with bench equipment including BERT, VNA, oscilloscopes, and protocol analyzers.
• Exposure to FPGA-based emulation and prototyping environments.
• Excellent written and verbal communication skills for effective collaboration across teams.
• Highly self-motivated, proactive, and strong in critical thinking and problem-solving.

Responsibilities

• Lead validation efforts across the post-silicon lifecycle from first silicon to production release.
• Provide strategic oversight and direction for validation plans and infrastructure.
• Oversee bench hardware/software requirements and ensure necessary tools are available.
• Develop custom RTL test logic to support targeted validation and IP understanding.
• Drive silicon bring-up and validate IP functionality and performance with data analysis.
• Coordinate cross-functional collaboration among design, verification, manufacturing, test, quality and marketing.
• Lead resolution of post-release customer issues with timely, effective solutions.

Skills

Leadership

Cross-functional teams

SerDes characterization

High-speed signaling

Signal integrity

Verilog/VHDL

FPGA design tools

Python

Perl

Statistics (JMP/R)

Bench testing

Education

Master's degree in Electrical Engineering

Tools

Python

Perl

JMP

R

BERT

VNA

Oscilloscopes

Protocol analyzers

Job description

Job Summary

As a Senior Manager in Silicon Design Validation, you lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products. Your role provides strategic oversight and technical direction across the full post-silicon lifecycle, from first silicon arrival to production release.

Responsibilities

• Technology Enablement Learning Culture: Fostering a learning environment where engineers gain hands‑on experience with FPGA architectures and foundational IP blocks such as SERDES (PMA/PCS), DDR memory (DDR4, LPDDR4, DDR5), DPHY, PLLs, DSPs, MIPI, Fabric, and I/O subsystems.
• Validation/Characterization Strategy Execution: Overseeing the validation and characterization of analog, digital, and mixed‑signal IPs, ensuring robust coverage from initial silicon bring‑up through production qualification.
• Planning Infrastructure Development: Guiding the development of validation plans, including bench hardware and software requirements, and ensure the team has the necessary tools and infrastructure to execute effectively.
• RTL Development for Test Enablement: Supervising the creation of custom RTL test logic to support targeted validation and characterization efforts, enabling deeper insight into IP behavior.
• Silicon Bring‑Up Debug Leadership: Driving the bring‑up of new silicon products, driving validation and debug activities to assess IP functionality and performance. This includes characterizing datasheet parameters, performing statistical analysis of measured data, and overseeing datasheet preparation.
• Cross‑Functional Collaboration: Acting as the central liaison between design, verification, manufacturing, test, quality, and marketing/application teams, ensuring alignment and smooth transition from silicon arrival to product release.
• Customer Support Issue Resolution: Providing leadership in resolving post‑release customer issues, coordinating with internal teams to ensure timely and effective solutions.

Qualifications

• 15+ years of experience in silicon validation, including 3-5 years in a leadership role.
• Master's degree or Bachelor's degree in Electrical Engineering with a strong passion for engineering and management in silicon design validation.
• Proven track record in managing complex validation projects and leading cross‑functional teams.
• Deep expertise in high‑speed SerDes interface characterization and protocol compliance testing (e.g., PCIe, Ethernet, SDI, CoaXpress, JESD204, MIPI D‑PHY, CSI/DSI-2, USB, DisplayPort, HDMI).
• Strong background in high‑speed board design, signal integrity evaluation, and debug.
• Proficient in Verilog/VHDL and FPGA design implementation using industry‑standard tools.
• Skilled in test automation development using Python and Perl.
• Solid understanding of statistical analysis and tools such as JMP and R.
• Hands‑on experience with bench equipment including BERT, VNA, oscilloscopes, and protocol analyzers.
• Exposure to FPGA‑based emulation and prototyping environments.
• Excellent written and verbal communication skills for effective collaboration across teams.
• Highly self‑motivated, proactive, and strong in critical thinking and problem‑solving.

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