SoC Implementation & Tapeout Engineer

ANANANT SYSTEMS PRIVATE LIMITED; Dadri; On-site; INR 1,800,000 - 3,200,000; Full time

Benefits offered by this job

Competitive CTC

ESOPs

Job summary

ANANANT SYSTEMS PRIVATE LIMITED is seeking a seasoned SoC Implementation & Tapeout Engineer to own end-to-end integration, synthesis, timing and power sign-off, DFT, and tapeout execution—from RTL handoff to GDSII delivery. The role reports to the Chief Architect/CTO.

We are building an AI-native DSP SoC for 5G/6G wireless, Edge AI inference, vision, camera, and radar applications, demanding hands-on expertise with tapeouts and post-silicon support.

Qualifications

• 5–15 years of hands-on experience in SoC implementation and tapeout.
• Experience with multi-domain power, clock, and UPF design.
• Proven track record of tapeouts at advanced nodes.
• Strong knowledge of sign-off for synthesis, timing, power, and DFT.

Responsibilities

• Integrate DSP datapath IPs, processor subsystems, memory controllers, and high-speed peripherals into the top-level SoC.
• Define and implement clock, reset, and power architectures across voltage domains.
• Drive hierarchical synthesis, STA timing closure, lint/CDC, and formal equivalence.
• Perform dynamic and static power analysis and optimization.
• Own DFT implementation including scan chain stitching and MBIST/LBIST.
• Manage full tapeout flow, ECOs, documentation, and foundry handoff.
• Support post-silicon bring-up and silicon characterization.

Skills

SoC Integration

Tapeout flow

Power Sign-off

Synthesis

STA

Education

B.Tech / M.Tech / PhD in Electronics/EE/CE

Tools

PrimeTime

DC/Genus

Spyglass

Job description

ANANANT SYSTEMS PRIVATE LIMITED | Full time

JobDescription: SoC Implementation & Tapeout Engineer

Department: Silicon Engineering — SoCImplementation

Experience: 5–15 years

Education: B.Tech / M.Tech / PhD —Electronics, Computer Engineering, or Electrical Engineering

Aboutthe Role

AnanantSystems is developing a proprietary AI-native DSP SoC targeting 5G/6G wireless,Edge AI inference, Vision AI, camera, video, and radar applications. We arelooking for an experienced SoC Implementation & Tapeout Engineer to ownend-to-end SoC integration, synthesis, timing & power sign-off, DFT, andtapeout execution — from RTL handoff to GDSII delivery and post-siliconsupport. The role reports directly to the Chief Architect / CTO.

KeyResponsibilities

• IntegrateDSP datapath IPs, processor subsystems, memory controllers, and high-speedperipherals (PCIe Gen3/4, USB3, JESD204B, MIPI CSI-2/DSI, DDR/LPDDR, etc.) intothe top-level SoC.
• Defineand implement clock, reset, and power architectures (UPF) across multiplevoltage domains.
• Drivehierarchical synthesis, STA timing closure (PrimeTime), lint/CDC checks, andformal equivalence across all design stages.
• Performdynamic & static power analysis and optimization to meet power budgets.
• OwnDFT implementation: scan chain stitching, MBIST/LBIST, JTAG TAP, and boundaryscan.
• Managecomplete tapeout flow — sign-off checklist, ECOs, documentation, and foundryhandoff.
• Supportpost-silicon bring-up, scan test debug, and silicon characterization.

Requirements

Expertlevel: Synthesis (DC/Genus), STA (PrimeTime), Lint & CDC (Spyglass), Power(UPF/Joules), Tapeout execution & sign-off.

Advancedlevel: DFT architecture, Formal Equivalence (Formality/Conformal), Clock/Resetdesign, Peripheral IP integration (PCIe, JESD204B, MIPI, DDR).

Strongunderstanding of FinFET nodes and multi-domain SoC integration.

MandatoryExperience

• Namedcontributor on at least 2 commercial tapeouts at 22nm or below.
• Directownership of sign-off (synthesis/timing/power/DFT) for at least one IP block orSoC subsystem through GDS handoff.
• Experiencein post-silicon debug or bring-up support.

StrongAdvantage

• Tapeoutexperience on heterogeneous SoCs with DSP + AI + Multimedia accelerators.
• Hands-onwork with high-speed SerDes (PCIe, JESD204B) and DDR/LPDDR controllers.
• PriorFinFET tapeouts (16nm/12nm/7nm).

WhatWe Offer

• Fullownership of implementation and tapeout of a next-generation AI-native DSP SoC.
• Directcollaboration with a Chief Architect having 20+ years of 4G/5G modem siliconexperience.
• Accessto advanced FinFET technology through foundry partnerships.
• CompetitiveCTC + meaningful ESOPs in an early-stage semiconductor startup.