SOC Engineering Senior Staff Engineer STA

Synopsys Inc; Hyderabad; On-site; INR 4,500,000 - 7,500,000; Full time

Job summary

Synopsys Inc in Hyderabad, India seeks an experienced STA engineer to drive timing closure for advanced nodes. You will own block-level timing, work with PD, synthesis, and verification, and push for robust signoff using SDC constraints and MMMC concepts.

The role emphasizes scripting automation (TCL/Python/Perl), cross-team collaboration, and high-quality deliverables under tight schedules.

Qualifications

• Bachelor’s or Master’s degree in Electronics/Electrical Engineering or related field.
• 8+ years of STA/timing closure experience; block ownership preferred.
• Proficiency with Synopsys tools: PrimeTime required; others preferred.
• Strong TCL scripting; Python/Perl for automation.

Responsibilities

• Enable timing closure for high-performance silicon.
• Improve first-pass success with robust constraints and signoff.
• Develop repeatable STA flows and automation.
• Lead timely analysis and deliverables ownership.

Skills

STA expertise

Constraints development

Scripting (TCL)

Python/Perl scripting

Team collaboration

Education

BE/BTech/MTech in Electronics/Electrical Engineering

Tools

PrimeTime

PrimePower/PT-PX

PrimeClosure/Tweaker

Fusion Compiler/ICC2 or DC

StarRC

Job description

Job Description:

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are a passionate and execution-focused Static Timing Analysis (STA) engineer with strong fundamentals in timing closure and signoff methodologies. You bring 8+ years of hands-on experience in STA and timing/power closure for advanced nodes (e.g., 16/12/10/7nm; exposure to 5nm is a plus). You are comfortable owning key timing deliverables for blocks and contributing to full-chip closure in collaboration with physical design, synthesis, and verification teams.

You have solid experience across the timing closure lifecycle—constraints development and validation, STA signoff, power analysis, and ECO support—and you enjoy solving complex timing issues under aggressive schedules. You communicate clearly, work effectively with global teams, and are motivated to improve productivity through scripting/automation (TCL/Python/Perl).

The Impact You Will Have:

• Enable predictable and high-quality timing closure for high-performance, low-power silicon.
• Improve first-pass success through robust constraints, clean signoff, and disciplined closure practices.
• Strengthen team execution by contributing to repeatable STA flows, automation, and cross-team alignment.
• Support successful project milestones through timely analysis, crisp communication, and ownership of deliverables.

The Team You’ll Be A Part Of:

You’ll join a team of backend and STA engineers focused on delivering robust timing and power closure solutions for leading silicon designs. The team values technical rigor, collaboration, and continuous improvement—working closely with experts across domains to help customers achieve their silicon goals.

What You’ll Need:

• Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or related field.
• 8+ years of relevant experience in STA / timing closure (block ownership expected; full-chip exposure preferred).
• Strong hands-on experience in:
• Constraints development/validation (SDC)
• STA signoff across modes/corners, including MMMC concepts
• Timing closure debugging and ECO validation
• Power analysis/support (PrimePower / PT-PX exposure preferred)
• Proficiency with Synopsys tools such as PrimeTime (required); PrimePower/PT-PX, PrimeClosure/Tweaker (preferred).
• Working knowledge/exposure to Fusion Compiler/ICC2 or DC, parasitic extraction concepts (e.g., StarRC), and signoff correlation (preferred).
• Strong scripting skills in TCL (required) and Python/Perl (preferred).
• Understanding of low-power and high-frequency design considerations (UPF awareness is a plus).

Who You Are:

• Self-driven, accountable, and comfortable working with minimal supervision on defined deliverables.
• Strong analytical and debugging skills with attention to detail.
• Clear communicator and effective collaborator across design, PD, and verification.
• Open to learning, improving flows, and sharing knowledge within the team.

The Team You’ll Be A Part Of:

You’ll join a team of backend and STA engineers focused on delivering robust timing and power closure solutions for leading silicon designs. The team values technical rigor, collaboration, and continuous improvement—working closely with experts across domains to help customers achieve their silicon goals.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share details on compensation and benefits during the hiring process.

Requirements: