Silicon Photonics PDK Development Engineer

Intel Technology India Pvt Ltd; Bengaluru; Hybrid; INR 1,500,000 - 2,000,000; Full time

Job summary

Intel Technology India Pvt Ltd in Bengaluru seeks an experienced Photonics PDK Development Engineer to enable production-grade silicon photonics PDKs, EPDA tools, and automation for design workflows.

You will collaborate across design, process, and software teams to build scalable PDKs, CI/CD pipelines, and verification flows, leveraging Calibre, IC Validator, and Cadence Virtuoso to accelerate tapeout readiness.

Qualifications

• Bachelor's degree in CS/EE/Photonics with 6+ years in EDA/EPDA/PDK development or related.
• Experience with photonic design flows and PIC design lifecycles.
• Proficiency with Cadence Virtuoso and SKILL; familiarity with DRC/LVS/ER C.
• Experience building and supporting PDKs, design enablement, and CI/CD pipelines.

Responsibilities

• Develop, validate, and maintain production-ready Silicon Photonics PDKs.
• Define EPDA tools, flows, and methods for PIC design and manufacturing.
• Develop and support physical verification using Calibre, IC Validator, and PVS.
• Design, develop, and maintain PCells, design automation, and IP.
• Apply AI/automation to accelerate design enablement workflows and quality.
• Build CI/CD pipelines for validation, packaging, and release of PDKs and tools.
• Collaborate with design, process, manufacturing, and foundry teams.

Skills

Python

Shell scripting

Unix/Linux

Education

Bachelor's degree in Computer Science / Electrical Engineering / Photonics

Master's degree (preferred)

Tools

Siemens Calibre

Cadence IC Validator

Cadence Virtuoso

PVS

Pegasus

Job description

Photonics PDK Development Engineer Job Details:

Job Description: The Role and Impact In this role, you will help shape the future of Intel's Silicon Photonics design ecosystem by enabling the development and deployment of production-ready PDKs, design automation methodologies, and verification solutions that support Intel's internal silicon photonic ecosystem. Through innovations in Physical Verification, PCell development, AI-assisted electronic-photonic design automation workflows, and automated CI/CD infrastructure, you will drive higher design quality, faster technology adoption, and improved engineering efficiency, directly contributing to Intel's leadership in high-performance optical connectivity and next-generation data center technologies.

Key Responsibilities

• Develop, validate, and maintain production-ready Silicon Photonics PDKs supporting internal product development and foundry enablement.
• Collaborate with PDK architects and domain experts to define and implement Electronic-Photonic Design Automation (EPDA) Tools, Flows, and Methods (TFM) for PIC design and manufacturing.
• Develop and support Physical Verification methodologies, including DRC, LVS, ERC, reliability checks, rule decks, and signoff flows using Siemens Calibre, Cadence Physical Verification solutions, and Synopsys IC Validator.
• Design, develop, and maintain PCells, design automation solutions, and reusable IP to improve PDK quality, scalability, and designer productivity.
• Apply AI and automation technologies to accelerate design enablement workflows, validation, engineering productivity, and quality improvement initiatives.
• Develop and maintain design enablement infrastructure, including cloud computing environments, EDA tool integrations, storage, licensing, and engineering productivity platforms.
• Build and support CI/CD pipelines for automated validation, testing, packaging, qualification, and release of PDKs, tools, and methodologies.
• Partner with design, process, manufacturing, and foundry teams to gather requirements and deliver robust design enablement solutions.
• Contribute to technical leadership, innovation, and continuous improvement initiatives across PDK, Physical Verification, Physical Design, design automation, and infrastructure development.

Minimum Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or Photonics with 6+ years of experience in Electronic Design Automation (EDA), Electronic-Photonic Design Automation (EPDA), PDK development, design enablement, CAD software development, or physical verification.
• Experience with custom analog, mixed-signal, and/or Photonic Integrated Circuit (PIC) design flows, including a strong understanding of the design-to-tapeout lifecycle.
• Experience developing and supporting physical verification solutions using industry-standard EDA platforms such as Siemens Calibre, Synopsys IC Validator (ICV), and Cadence PVS/Pegasus.
• Strong proficiency with Cadence Virtuoso design environments, including SKILL programming, design automation, PCell development, and flow customization.
• Strong programming and scripting skills in Python and Linux shell environments (tcsh, bash, Tcl, or equivalent).
• Experience working in Unix/Linux environments, software development methodologies, version control systems, and automation frameworks.
• Familiarity with DRC, LVS, ERC, parasitic extraction, verification methodologies, and automated validation flows.
• Strong technical problem-solving, debugging, and collaboration skills in a multidisciplinary engineering environment.

Preferred Qualifications

• Master's degree with 4+ years of relevant experience, or Ph.D. with 2+ years of relevant experience, in Electronic Design Automation (EDA), Electronic-Photonic Design Automation (EPDA), Silicon Photonics, PDK development, Physical Verification, or related fields.
• Experience developing, validating, and releasing production-ready Silicon Photonics PDKs, PCells, and design enablement infrastructure.
• Experience developing Electronic-Photonic Design Automation (EPDA) Tools, Flows, and Methods (TFM) for analog, mixed-signal, and photonic design environments.
• Advanced expertise in Cadence Virtuoso design flows, custom layout automation, SKILL development, PCell architecture, schematic-driven layout (SDL), and design environment customization.
• Experience developing advanced parametric cells (PCells) and layout automation solutions for Photonic Integrated Circuit (PIC) design, including curvilinear - PCell development and customization using Cadence Virtuoso and CurvyCore technologies.
• Experience developing and validating physical verification rule decks using Siemens Calibre SVRF/TVF, Synopsys ICV, and Cadence PVS/Pegasus.
• Experience with hierarchical PIC design, layout automation, floorplanning, and design productivity solutions.
• Experience building CI/CD pipelines, automated regression frameworks, release automation systems, and validation infrastructure for PDKs and design tools.
• Experience supporting engineering infrastructure, cloud computing environments, EDA deployment, storage, licensing, and scalable compute platforms.
• Experience applying AI/ML technologies to design automation, verification, engineering productivity, or workflow optimization.
• Familiarity with foundry enablement, semiconductor manufacturing processes, technology qualification, and multi-foundry design ecosystems.
• Demonstrated ability to influence technical direction, mentor engineers, and collaborate effectively across design, process, manufacturing, and software development organizations.

Job Type and Location

Job Type: Experienced Hire

Shift: Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Work Model for this Role

Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Additional Information

* Job posting details (such as work model, location or time type) are subject to change.

* ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.

We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.