Silicon Design Verification Engineer

Sunrise Biztech Systems; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Part time

Job summary

Sunrise Biztech Systems Pvt. Ltd. is hiring a Silicon Design Verification Engineer in Bangalore for a 12-month contract.

The role requires 8+ years of full-time experience in verification of ARM-based DUTs and ARM IPs, including Cortex-A/Cortex-R families, SMMU, GIC, and related components. The candidate should be proficient in SystemVerilog, UVM, and C for digital design verification, with strong code coverage techniques and ABV experience.

Qualifications

• 8+ years of full-time experience in design verification on DUTs in ARM architecture.
• Experience with verification on ARM IPs such as Cortex-A cores/DSU, Cortex-R cores/DSU, SMMU, GIC, etc.
• Proficiency in system Verilog, UVM, and C for digital design verification.
• Knowledge of code coverage closing lines, expressions and branches.
• Experience with ABV and constrained random environments.

Skills

SystemVerilog

UVM

C for verification

ARM architecture familiarity

Code coverage analysis

ABV (assertion-based verification)

Constrained random verification

DUT verification on ARM IPs

Tools

SystemVerilog

UVM

C

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our top leading semiconductor client. If you're interested and your experience matches the requirement, we'd love to hear from you.

Job Title: Silicon Design Verification Engineer

Location: IN07-IN, Bangalore-Technostar B3

Duration: 12 Months Contract

Required Experience:

• 8 or more years of full-time experience in design verification on DUTs in ARM architecture
• Previous working experience on design verification on ARM IPs, such as Cortex-A cores/DSU, Cortex-R cores/DSU, SMMU, CMN, GIC, Coresight, NIC/NOC, PCK, STM, etc.
• Proficiency in system Verilog, UVM, and C for digital design verification
• Code coverage analysis and how to close line, expression and branch coverage
• Experience with assertion-based verification (ABV)
• Detailed knowledge of how to code coverpoints and closing functional coverage in a constrained random environment