Senior Staff - SOC RTL Design Engineer

TylSemi, Inc.; Karnataka; Hybrid; INR 4,500,000 - 7,000,000; Full time

Job summary

TYLsemi, Inc. is seeking an experienced RTL Designer to develop high-performance, power-efficient digital designs for next‑gen SoCs and chiplets targeting AI/HPC and networking applications.

The role requires deep RTL expertise, micro-architecture know‑how, and integration of high-speed interfaces, with emphasis on quality, performance, and first-time silicon success. 12+ years in digital IC design preferred.

Qualifications

• 12+ years of digital IC design experience with ownership of infrastructure blocks (clocking, power management, resets).
• Familiarity with embedded microcontroller integration: memory maps, boot ROM, interrupts, firmware bring-up.
• Experience with reset-domain architecture and reset synchronizer design in multi-power-domain chips.
• Strong SystemVerilog skills for infrastructure RTL: clock-gating, power FSMs, scan muxing, BIST controllers.

Responsibilities

• Specify and own the reset sequencing architecture.
• Own the secure boot and fuse micro architecture and design.
• Coordinate with subsystem leads on reference clock distribution and CDC points.
• Collaborate with firmware on hardware/software interface (interrupts, timer, UART/JTAG, DMA).
• Own clock-gating strategy and sign-off methodology for dynamic power reduction.
• Define chip-level power-domain plan and where level-shifters/isolation are required.
• Own embedded management processor subsystem: boot sequence, SRAM/ROM sizing, firmware interface.
• Define management register map for firmware configuration and telemetry.
• Specify thermal monitoring integration and readout paths to management processor.
• Drive UPF/CPF power intent authoring and sign-off with physical design team.

Skills

RTL Design

SystemVerilog

Power Management

Reset Architecture

DFT

Firmware Bring-up

Education

BS in Electrical Engineering

MS in Electrical Engineering

MS in Computer Engineering

Job description

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem:how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds thechiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem:how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds thechiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

Moore's Law is dead.2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

Custom silicon is now mainstream.Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

IO and power are the bottleneck.Solve hard problems and provide something which is a category in itself.

Translation:We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

If you have an idea, we test it. If it works, we ship it. No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

US team: Bay Area preferred, but we hire the best people regardless of location India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

Ownership mindset.You're not here to execute someone else's roadmap. You're here to define it.

Bias for action.We move fast. Analysis paralysis doesn't fly here.

Deep technical expertise.This is hard engineering. We need people who've shipped real silicon and debugged real hardware.

Low ego, high standards.We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

The market is real.AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

The team has done this before.We've built and exited semiconductor companies at scale. This isn't our first rodeo.

The traction is de-risked.We have LOIs, strategic investors, and a clear path to revenue.

The work is consequential.You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet.Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We are looking for a highly skilledRTL Designerto develop high-performance, scalable, and power-efficient digital designs for next-generation SoCsand ChipletstargetingAI, HPC, and Networking applications. This role requires deepexpertisein RTL design, micro-architecture, and integration of high-speed interfaces, along with a strong focus onquality, performance, and first-time silicon success.

What You’ll Do

• Specifyand ownthe reset sequencing architecture.
• Own the secure boot and fuse micro architecture and design.
• Coordinatewith thesubsystem leads on reference clockdistribution,clock-domain crossing points at subsystem interfaces.
• Collaborate with the firmware team to define the hardware/software interface: interrupt controller, timer, UART/JTAG debug port, and any DMA or mailbox channels
• Own the clock-gating implementation strategy: coarse-grain vs. fine-grain gating, ICG cellselection, and sign-offmethodologyfor dynamic power reduction.
• Define the chip-level power-domain plan: which blocks share supplies, where level-shifters and isolation cells arerequired, and how power states map to the PCIe and UCIe link power management protocols.
• Own the on-chip power management logic: power-state machine, supply sequencing, voltage regulator integration, and the firmware interface for runtime power control.
• Drive power intent (UPF/CPF) authoring and sign-off,coordinatingwithphysical designteamon power-domain floorplan, always-on routing, and isolation verification.
• Own the embedded management processor subsystem: processor integration, on-chip SRAM and ROM sizing, boot sequence, fuse and OTP interface, and the firmware execution environment.
• Define the management register map: the address space through which firmware configures operating modes, reads telemetry, controls power states, and manages DFT operations.
• Specify thermal monitoring integration: on-die temperature sensor placement, readout path to the management processor, and thermal throttling hooks.

What We’re Looking For

12+ years of digital IC design, with at least 5 years owning chip infrastructure — clocking, power management,resetor DFT — at block-lead or subsystem-owner level. Familiarity with embedded microcontroller integration: memory maps, boot ROM, interrupt controllers, and firmware bring-up at the hardware level. Experience with reset-domain architecture and reset synchronizer design in multi-power-domain chips. StrongSystemVerilogskills for infrastructure RTL: clock-gating cells, power FSMs, scan-enablemuxing, and BIST controllers. BS/MS in Electrical Engineering, Computer Engineering, or equivalent.

Good to Have

Background integrating a RISC-V or ARM Cortex-M class processor as a management/configuration engine in a non-CPU chiplet. Exposure tohardware security: secure boot, anti-tamper fuse programming,or relatedinfrastructure.