Senior Staff Low Power Verification Applications Engineer

Synopsys, Inc.; Bengaluru; On-site; INR 4,000,000 - 8,000,000; Full time

Job summary

Synopsys, Inc. in Bengaluru is seeking a seasoned Low-Power Verification expert to lead deployments of VCS NLP at key customer sites, focusing on UPF power models and multi-domain SoCs.

You will translate customer challenges into product requirements for R&D, mentor teams, and push advances in IEEE 1801-based verification and power-aware simulation practices.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline.
• 8 to 12 years of hands-on experience in product engineering, applications engineering, or ASIC/SoC verification with a focus on low-power methodologies.
• Deep expertise in IEEE 1801 (UPF) including power domains, power state tables, retention strategies, isolation, level shifters, and power sequencing.
• Strong proficiency with SystemVerilog, UVM, assertions (SVA), coverage-driven verification, and RTL simulation flows.
• Proven ability to debug complex multi-domain SoC verification environments and trace issues across design, verification testbenches, and power intent specifications.
• Experience with Synopsys VCS, VCS NLP, or similar power-aware simulation tools is a strong plus.

Responsibilities

• Lead technical deployments of VCS NLP at strategic customer sites, working directly with verification teams to implement power-aware simulation flows for complex SoCs and IP blocks.
• Debug and resolve challenging low-power verification issues involving UPF modeling, power state transitions, retention logic, isolation strategies, and corruption scenarios across multi-domain designs.
• Act as the technical bridge between customers and Synopsys R&D, translating real-world verification challenges into product requirements and influencing the VCS NLP roadmap.
• Develop and deliver best-practice methodologies, reference flows, application notes, and training materials for IEEE 1801 based verification
• Provide technical mentorship to customer teams and internal engineers on advanced low-power verification techniques and UVM integration with power-aware simulation

Skills

Power-aware verification

SystemVerilog

UVM

Assertions (SVA)

RTL simulation

Debug multi-domain SoC verification

Power UPF/IEEE 1801

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline

Tools

Synopsys VCS

VCS NLP

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of low-power verification, where a missed isolation cell or a poorly modeled power state transition can cost months of debug time or worse, a silicon respin. You understand that UPF is not just a specification to check off, it is the contract between design intent and verification reality, and you have debugged enough power domain crossings to know where that contract usually breaks.

You are equally comfortable sitting with a customer's verification team walking through a complex power state table corruption scenario and sitting with R&D explaining why a specific customer use case needs to drive the next product enhancement. When a customer says 'VCS NLP is not working,' you dig until you find whether it is a methodology gap, a tool limitation, or a misunderstood UPF construct. At Synopsys, you will work directly with the semiconductor companies building the next generation of AI, mobile, and automotive SoCs.

What You'll Be Doing

• Lead technical deployments of VCS NLP at strategic customer sites, working directly with verification teams to implement power-aware simulation flows for complex SoCs and IP blocks
• Debug and resolve challenging low-power verification issues involving UPF modeling, power state transitions, retention logic, isolation strategies, and corruption scenarios across multi-domain designs
• Act as the technical bridge between customers and Synopsys R&D, translating real-world verification challenges into product requirements and influencing the VCS NLP roadmap
• Develop and deliver best-practice methodologies, reference flows, application notes, and training materials for IEEE 1801 based verification
• Provide technical mentorship to customer teams and internal engineers on advanced low-power verification techniques and UVM integration with power-aware simulation

The Impact You Will Have

• Enable semiconductor companies to achieve robust pre-silicon verification of advanced power management architectures, reducing the risk of costly power-related silicon bugs
• Accelerate customer adoption and time-to-productivity with VCS NLP, directly impacting their ability to meet aggressive tapeout schedules
• Shape the evolution of Synopsys low-power verification solutions by providing R&D with prioritized, real-world customer requirements
• Build verification methodologies that become industry reference standards, influencing how teams across multiple companies approach power-aware verification
• Strengthen Synopsys customer relationships by becoming the trusted technical advisor for their most critical low-power verification initiatives

What You'll Need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical discipline
• 8 to 12 years of hands-on experience in product engineering, applications engineering, or ASIC/SoC verification with a focus on low-power methodologies
• Deep expertise in IEEE 1801 (UPF) including power domains, power state tables, retention strategies, isolation, level shifters, and power sequencing
• Strong proficiency with SystemVerilog, UVM, assertions (SVA), coverage-driven verification, and RTL simulation flows
• Proven ability to debug complex multi-domain SoC verification environments and trace issues across design, verification testbenches, and power intent specifications
• Experience with Synopsys VCS, VCS NLP, or similar power-aware simulation tools is a strong plus

Who You Are

• You can walk into a customer war room during a critical tapeout issue, quickly assess a failing power state scenario, and guide the team to root cause without creating confusion
• You know the difference between a UPF syntax error and a fundamental methodology gap, and you can explain both to a stressed verification lead in terms that help them move forward
• You push back constructively when a customer request does not align with best practices, offering alternative approaches rather than just saying no
• You can translate a complex technical limitation into a clear product requirement that R&D can prioritize and implement

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.