Senior Staff- Formal Verification Specialist

Synopsys, Inc.; Bengaluru; On-site; INR 15,00,000 - 25,00,000; Full time

Job summary

A leading semiconductor design company in Bengaluru is looking for a Senior Staff - Formal Verification Specialist. You will develop and validate advanced formal verification tools and play a crucial role in ensuring reliability and performance in chip design. Ideal candidates have over 8 years of experience in EDA tool validation and possess a strong background in scripting, digital design, and formal methods. Join a dynamic team that thrives on innovation and collaboration.

Benefits

Comprehensive health benefits

Financial wellness offerings

Qualifications

• 8+ years of experience in formal verification or EDA tool validation.
• Hands-on experience with formal verification tools.
• Strong knowledge of formal methods, SystemVerilog Assertions, and digital design fundamentals.

Responsibilities

• Develop comprehensive test plans for formal verification tools.
• Validate advanced features of EDA tools.
• Create and execute robust test cases and regression suites.
• Analyze tool behavior and communicate findings to R&D.

Skills

Analytical problem-solving

Debugging skills

Collaboration

Proficiency in scripting languages

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Science

Tools

Synopsys VC Formal

Job description

Job Title: Senior Staff- Formal Verification Specialist

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate engineer with a keen interest in the intricate world of formal verification and EDA tool validation. You thrive on solving complex technical problems and are motivated by the challenge of ensuring the highest standards for cutting-edge verification solutions. With a strong background in digital design and formal methods, you are well-versed in scripting and comfortable in Unix/Linux environments. You bring a collaborative spirit, excellent analytical abilities, and a commitment to continuous learning and improvement. Your experience ranges from hands-on tool validation to partnering with R&D teams, and you are eager to influence the development of industry-leading products. You value working in diverse, cross-functional teams and appreciate the opportunity to share your expertise and learn from others. Adaptable and detail-oriented, you excel in fast-paced environments and enjoy staying abreast of the latest trends in formal verification. Above all, you are driven by the desire to make a tangible impact on the future of silicon design and verification.

What You’ll Be Doing

• Develop comprehensive test plans for formal verification tools and innovative methodologies.
• Validate advanced features of EDA tools such as Synopsys VC Formal, including Property Verification (FPV), Sequential Equivalence (SEQ), and Connectivity Checking.
• Create and execute robust test cases and regression suites to thoroughly assess tool functionality and performance.
• Analyze tool behavior, debug complex issues, and effectively communicate findings to the R&D team for resolution and improvement.
• Collaborate closely with cross-functional teams, including R&D, application engineers, and product management, to define and enhance tool features.
• Stay current with the latest formal verification methodologies, industry standards, and emerging trends to drive innovation in tool development.

The Impact You Will Have

• Ensure the reliability and performance of industry-leading formal verification tools used globally in chip design.
• Drive quality improvements that directly influence customer success and satisfaction.
• Contribute to faster time-to-market for advanced silicon solutions by validating and enhancing verification tool capabilities.
• Empower cross-functional teams with actionable insights and feedback that shape product direction and innovation.
• Advance the state-of-the-art in formal verification methodologies, helping Synopsys maintain its leadership position.
• Play a pivotal role in delivering robust, scalable solutions for the most demanding semiconductor applications.

What You’ll Need

• Bachelor\'s or Master\'s degree in Electrical Engineering, Computer Science, or related discipline.
• 8+ years of experience in formal verification or EDA tool validation.
• Hands-on experience with formal verification tools such as Synopsys VC Formal.
• Strong knowledge of formal methods, SystemVerilog Assertions (SVA), and digital design fundamentals.
• Proficiency in scripting languages (Python, Perl, Tcl) within Unix/Linux environments.

Who You Are

• Analytical problem-solver with strong debugging skills and attention to detail.
• Effective communicator, able to convey technical concepts clearly across teams.
• Collaborative team player with a proactive approach to sharing insights and feedback.
• Adaptable and eager to learn new technologies and methodologies.
• Driven by curiosity, innovation, and a commitment to excellence.

The Team You’ll Be A Part Of

You will join a dynamic and diverse engineering team focused on developing and validating world-class formal verification solutions. The team thrives on innovation, collaboration, and technical rigor, working closely with R&D, product management, and application engineers to deliver impactful products. You’ll be part of a supportive environment that values continuous learning, open communication, and the pursuit of excellence in every aspect of tool development.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.