Senior Staff Engineer, Low Power & Formal Equivalence Verification (VCLP / FEV)

Renesas; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Benefits offered by this job

Competitive benefits package

Job summary

Renesas is seeking a Senior Staff Engineer to lead Low Power (Power Intent) and Formal Equivalence Verification (FEV/LEC) for complex ASIC/SoC programs in Bengaluru. You will define UPF/CPF power intent and ensure correct low‑power implementation across RTL, synthesis, DFT, and tapeout.

This role requires close collaboration with Architecture, RTL, Verification, Synthesis, DFT, STA, and Physical Design teams to guarantee functional correctness, power integrity, and successful tapeouts on

Qualifications

• Strong hands-on experience with low-power design and UPF/CPF.
• Extensive experience with formal verification and RTL-to-tapeout flows.
• Experience in ASIC/SoC implementation and signoff processes.

Responsibilities

• Lead low-power architecture and power intent definition using UPF/CPF.
• Drive formal equivalence verification across RTL to tapeout.
• Collaborate with cross-functional teams to ensure power-aware signoff.
• Develop automation for LVL verification and issue tracking.

Skills

Tcl scripting

Python scripting

Perl scripting

Shell scripting

Debugging

Analytical thinking

Problem solving

Education

Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering

Tools

FEV/LEC tools

Synthesis tools

DFT tools

Job description

Senior Staff Engineer, Low Power & Formal Equivalence Verification (VCLP / FEV)

• Full-time
• Employment Type: Regular (PERM)
• Remote Work Available: No

Renesas is a global semiconductor leader shaping the backbone of next‑generation automotive, industrial, cloud, and IoT innovation. With over $9.3billion in annual revenue (2024) and a world‑class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category‑defining breakthroughs. The company’s footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovative engine. As Japan’s semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real‑world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. For ambitious problem‑solvers who want to work on meaningful, systems‑level challenges with huge industry leverage, Renesas offers the scale, stability, and strategic clarity of a market leader—paired with the transformative momentum of a company reinventing how the world computes, connects, and electrifies.

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

We are seeking a highly motivated and experienced engineer to lead Low Power (Power Intent) and Formal Equivalence Verification (FEV/LEC) activities for complex ASIC/SoC programs. The ideal candidate will be responsible for defining and signing off power intent (UPF/CPF), ensuring correct low‑power implementation across all design stages, and driving formal equivalence verification from RTL through synthesis, DFT, implementation, and ECOs to tapeout.

This role requires close collaboration with Architecture, RTL, Verification, Synthesis, DFT, STA, Physical Design, PDN, and Signoff teams to ensure functional correctness, low‑power integrity, and successful tapeout execution.

Key Responsibilities

Low Power / Power Intent

• Define, develop, and maintain low‑power architecture and power intent using UPF/CPF.
• Own power‑domain and power‑state specifications across IP, subsystem, and chip‑level designs.
• Drive implementation and integration of isolation, retention, level shifters, and power‑switch methodologies.
• Debug and resolve power‑intent issues across RTL, synthesis, implementation, and ECO stages.
• Collaborate with cross‑functional teams to ensure power‑aware constraints, methodologies, and signoff checks.
• Drive low‑power issue closure and tapeout readiness.

Formal Equivalence Verification

• Execute formal equivalence checks at key design milestones:
  • RTL Synthesis
  • Synthesis DFT
  • DFT Physical Design
  • Pre‑ECO Post‑ECO
• Analyze and debug equivalence failures related to constraints, mapping, low‑power insertion, DFT logic, and ECO changes.
• Drive issue resolution with clear ownership and closure tracking.
• Validate RTL, netlists, library models, constraints, and ECO patches for functional equivalence.
• Generate signoff‑quality reports and support milestone/tapeout reviews.
• Develop automation and reusable methodologies to improve verification efficiency and quality.
• Create scripts and checks for low‑power validation, equivalence verification, and issue tracking.
• Drive continuous improvements in low‑power and formal verification flows.

Qualifications

• Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.
• 10-15 years of experience in ASIC/SoC implementation, low‑power design, or formal verification.
• Strong expertise in UPF/CPF-based low‑power methodologies.
• Deep understanding of power domains, power states, isolation, retention, level shifters, and power gating.
• Hands‑on experience with Formal Equivalence Verification (FEV/LEC) tools and methodologies.
• Strong understanding of synthesis, DFT, STA, ECO, and implementation flows.
• Proficiency in Tcl, Python, Perl, or Shell scripting.
• Excellent debugging, analytical, and problem‑solving skills.

Preferred Qualifications

• Experience with advanced-node technologies (7nm and below).
• Knowledge of Physical Design, PDN, STA, and signoff methodologies.
• Experience supporting full‑chip SoC tapeouts.
• Strong collaboration skills and experience working across global design teams.

Why Join Us?

Join a high-performance engineering team developing next‑generation semiconductor products. You will play a critical role in ensuring low‑power integrity and functional correctness across the complete RTL‑to‑GDSII flow, directly contributing to successful tapeouts on advanced technology nodes.

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read ourDiversity & Inclusion Statement .