Principal Engineer / Manager - Design Verification

Renesas Electronics India Pvt Ltd; Bengaluru; On-site; INR 4,500,000 - 9,000,000; Full time

Job summary

Renesas Electronics India Pvt Ltd in Bengaluru seeks a Principal Engineer/Manager, Design Verification to lead a team responsible for functional verification of complex digital IPs, subsystems, and SoCs.

The role requires deep verification methodologies, strong people leadership, and a track record of delivering silicon on schedule, with close collaboration across design, architecture, firmware, emulation, and validation teams.

Qualifications

• 15+ years in Design Verification with 3–5 years in leadership.
• Deep expertise in SystemVerilog UVM, assertions and coverage.
• Experience verifying complex SoCs, IPs or subsystems.

Responsibilities

• Own verification strategy, planning, execution and sign-off for complex SoCs.
• Define verification plans aligned with architectural specs and product requirements.
• Drive adoption of UVM, SystemVerilog, assertions and coverage-driven verification.
• Establish metrics and benchmarks to ensure robust delivery.
• Lead root-cause analysis and resolution of critical issues.
• Build, mentor and retain a high-performing verification team.

Skills

People leadership

Verification strategy

Cross-functional collaboration

UVM/SystemVerilog

Automation & productivity

Education

Bachelor's or Master's in Electronics Engineering

Tools

SystemVerilog UVM

Assertions

Formal verification

Job description

Principal Engineer/Manager - Design Verification

Renesas is a global semiconductor leader shaping the backbone of next‑generation automotive, industrial, cloud, and IoT innovation. With over $9.3 billion in annual revenue (2024) and a world‑class team of 22,700+ employees, Renesas operates at scale while retaining the agility to drive category‑defining breakthroughs. The company’s footprint spans more than 30 countries, enabling deep customer proximity and a uniquely global innovative engine. As Japan’s semiconductor powerhouse and a top global player in microcontrollers, analog, and power technologies, Renesas delivers real‑world impact across EVs, smart factories, renewable energy infrastructure, and edge intelligence. For ambitious problem‑solvers who want to work on meaningful, systems‑level challenges with huge industry leverage, Renesas offers the scale, stability, and strategic clarity of a market leader—paired with the transformative momentum of a company reinventing how the world computes, connects, and electrifies. Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

Job Description

We are seeking an experienced and highly motivated Principal Engineer/Manager, Design Verification to lead a team responsible for functional verification of complex digital IPs, subsystems, and SoC solutions. The ideal candidate will have deep expertise in verification methodologies, strong people leadership skills, and a proven track record of delivering high‑quality silicon products on schedule. This role requires close collaboration with architecture, design, firmware, emulation, validation, and program management teams to drive verification excellence and achieve first‑silicon success.

Key Responsibilities

• Own verification strategy, planning, execution, and sign‑off for complex SoCs and SoC Subsystems.
• Define comprehensive verification plans aligned with architectural specifications and product requirements.
• Drive adoption of industry‑standard verification methodologies such as UVM, SystemVerilog, Assertions, Coverage‑Driven Verification, Formal Verification, and Emulation.
• Establish verification metrics, coverage goals, and quality benchmarks to ensure robust product delivery.
• Review verification architectures, testbench frameworks, reusable components, and coverage models.
• Lead root cause analysis and resolution of critical functional issues.
• Build, mentor, and retain a high‑performing verification team.
• Manage team goals, performance reviews, career development, and succession planning.
• Foster a culture of technical excellence, accountability, collaboration, and innovation.
• Drive recruitment and onboarding of verification engineers across experience levels.
• Partner with Design, Architecture, Validation, DFT, Firmware, and Program Management teams throughout the product lifecycle.
• Track project schedules, risks, dependencies, and resource planning.
• Provide regular status updates to senior leadership on project execution and quality metrics.
• Ensure timely achievement of verification milestones and tape‑out readiness.
• Define and implement best practices for verification productivity and reuse.
• Drive automation initiatives to improve efficiency and reduce turnaround time.
• Improve regression methodologies, debug workflows, and coverage closure processes.
• Promote continuous improvement through post‑silicon feedback and lessons learned.

Qualifications

• Bachelor's or master's degree in Electronics Engineering, Electrical Engineering.
• 15+ years of experience in Design Verification with at least 3‑5 years in technical leadership or people management roles.
• Strong expertise in:
  • System Verilog UVM methodology
  • Functional coverage and assertions
  • Verification planning and execution
  • Simulation, emulation, and formal verification techniques
• Experience verifying complex digital designs, IPs, subsystems, or SoCs.
• Strong debugging skills and understanding of microarchitecture.
• Experience with scripting languages such as Python, Perl, Tcl, or Shell.
• Proven experience driving projects from specification through silicon validation.

Preferred Qualifications

• Experience in Automotive SoCs and MCUs.
• Familiarity with safety standards such as ISO26262.
• Knowledge of mixed‑signal verification methodologies.
• Experience with FPGA prototyping and emulation platforms.
• Experience managing geographically distributed teams.
• Strong stakeholder management and communication skills.

Key Competencies

• Proven technical expertise in Verification
• People Leadership
• Strategic Thinking
• Tracking of deliverables and guiding junior members of the team
• Problem Solving
• Cross‑Functional Collaboration
• Decision Making
• Talent Development
• Continuous Improvement

Success Measures

• Achievement of verification coverage and quality targets.
• On‑time project execution and tape‑out readiness.
• Reduction in escaped bugs and post‑silicon issues.
• Team engagement, capability development, and retention.
• Increased verification reuse, automation, and productivity.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

Experience Level

Senior Level

Equal Opportunity

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .