Staff Applications Engineer ( ASIC, Physical Design, TCL / Python )

Synopsys, Inc.; Bengaluru; On-site; INR 4,500,000 - 6,500,000; Full time

Job summary

Synopsys, Inc. in Bengaluru is seeking a seasoned ASIC/physical design engineer with 5+ years of hands-on experience in RTL-to-GDS flows and timing closure. You will work with Fusion Compiler, Formality, and PrimeTime to drive design closure, power optimization, and performance at advanced nodes.

You will debug complex timing and congestion issues, build TCL/Python automation, and partner with senior engineers to tape out high-performance chips for AI, automotive, and networking applications.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with hands-on ASIC/physical design experience.
• Direct experience with RTL-to-GDS implementation flows including synthesis, place-and-route, timing closure, and physical design optimization.
• Proficiency with Fusion Compiler, ICC2, Formality, and PrimeTime; TCL and Python scripting to automate tasks.

Responsibilities

• Assist customers through physical design implementation and design closure using Synopsys tools.
• Debug timing, power, congestion, routing, and runtime optimization at advanced nodes (5nm and below).
• Provide technical guidance on synthesis, place-and-route, timing closure, and power optimization.
• Develop automation scripts in TCL to streamline workflows and improve turnaround time.
• Collaborate with R&D to reproduce issues, validate tool behavior, and feed use cases back to product development.
• Present technical solutions to senior customer engineers and design leads during critical phases.
• Support RTL-to-GDS flow from implementation through signoff and tapeout readiness.

Skills

RTL-to-GDS flow

Timing closure

Python scripting

Scripting TCL

AI-assisted workflows

Customer collaboration

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Fusion Compiler

ICC2

Formality

PrimeTime

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent the last few years deep in the RTL2GDS flow, and you know that the real work happens in the messy middle where verification meets implementation and theory meets timing closure. You understand that a clean ECO is not about clever tricks, it is about knowing the tools well enough to make the right call under pressure when a customer's tapeout schedule depends on it.

You are comfortable debugging complex place-and-route issues, timing convergence challenges, congestion problems, power optimization opportunities, and physical implementation bottlenecks using Fusion Compiler. Advanced nodes do not intimidate you because you have seen what breaks at 5nm and 3nm, and you have learned how to anticipate and solve those challenges.

You can work directly with senior design engineers and technical leads, understand their implementation constraints, and provide practical solutions that help them reach tapeout goals. Knowledge of complementary tools such as Formality, PrimeTime, and other Synopsys signoff solutions is highly valued.

You also embrace modern AI-assisted workflows and understand how to leverage AI tools to improve productivity, accelerate debug, automate repetitive tasks, and deliver faster, more effective customer support. At Synopsys, you will work directly with customers building the chips that power everything from AI accelerators to automotive systems, and the solutions you deliver will matter.

What You'll Be Doing

• Support customers through physical design implementation and design closure using Synopsys tools
• Debug complex design challenges across timing, power, area, congestion, routing, and runtime optimization at advanced process nodes including 5nm and below
• Help customers achieve implementation closure while meeting aggressive tapeout schedules and design quality requirements
• Provide technical guidance on best practices for synthesis, place-and-route, timing closure, power optimization, and advanced implementation methodologies
• Build and maintain automation scripts in TCL to streamline workflows and improve turnaround time for customer engagements
• Utilize AI-powered tools and workflows to improve productivity, accelerate issue resolution, and enhance customer support effectiveness
• Collaborate with internal R&D teams to reproduce customer issues, validate tool behavior, and feed real-world use cases back into product development
• Present technical solutions and recommendations to senior customer engineers and design leads during critical project phases
• Work across the full RTL-to-GDS flow, from implementation through signoff and tapeout readiness

The Impact You Will Have

• Enable customers to achieve first-pass silicon success on high-performance chips powering AI, automotive, networking, and mobile applications
• Improve customer productivity by helping them maximize the value of Fusion Compiler and advanced implementation methodologies
• Reduce customer tapeout risk by identifying and resolving implementation challenges early in the design cycle
• Influence Synopsys tool development by bringing real customer pain points and use cases directly to engineering teams
• Accelerate customer productivity through automation, AI-assisted workflows, and best-practice methodologies that become adopted across their organizations
• Build long-term technical relationships with leading semiconductor companies in the region, becoming their trusted advisor for implementation and design closure challenges
• Help shape how advanced-node designs are implemented by solving problems at the edge of what today's tools and methodologies can achieve
• Strengthen Synopsys's reputation as the partner that shows up when the hard problems need solving

What You'll Need

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with at least 5 years of hands-on ASIC, physical design, implementation, or CAD engineering experience
• Direct experience with RTL-to-GDS implementation flows, including synthesis, place-and-route, timing closure, and physical design optimization
• Strong working knowledge of Fusion Compiler, ICC2, or equivalent digital implementation tools
• Understanding of timing, power, congestion, routing, and design closure methodologies
• Working knowledge of Formality, PrimeTime, or related EDA tools is a strong advantage
• Proficiency in scripting with TCL and Python to automate design tasks and improve workflow efficiency
• Experience with advanced process nodes (7nm and below) is a strong plus, especially if you have worked through design closure challenges at those nodes
• Demonstrated ability to leverage AI tools and automation technologies to improve engineering productivity and problem-solving effectiveness
• Business-level English proficiency with the ability to communicate technical concepts clearly in written and spoken form
• Willingness to engage directly with customers, including senior engineers and design managers, in both remote and onsite settings

Who You Are

• You can explain a complex timing, congestion, or implementation issue to a customer in two sentences without losing the technical nuance that matters
• When a customer escalation comes in at 4pm on a Friday, you do not panic, you prioritize, engage the right people, and drive the issue to resolution
• You do not wait for perfect documentation or complete requirements, you ask the right questions, make reasonable assumptions, and move forward
• Detail matters to you, whether it is a script that needs to handle edge cases or a customer presentation that has to be technically accurate and clear
• You continuously look for ways to improve efficiency and know how to leverage AI, automation, and analytics tools to increase productivity and accelerate problem-solving
• You are comfortable working across time zones and cultures, adjusting your communication style to match the audience without losing clarity
• You treat customer problems like they are your own, not because it is your job, but because you care about delivering solutions that actually works

The Team You'll Be Part Of

Join a dynamic team focused on Fusion Compiler deployment, advanced-node implementation, design closure, and achieving best-in-class PPA results. We value collaboration, continuous learning, innovation, and helping customers solve their most challenging physical design problems.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.