Senior Product Engineer - Synthesis

Siemens España; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Siemens EDA in Bangalore is seeking a seasoned engineer to lead a team focused on logic synthesis for digital IC designs. You will drive improvements in RTL2GDSII flows, mentor engineers, and collaborate with R&D to shape the roadmap for next-generation synthesis solutions.

You should have hands-on experience with Verilog, SystemVerilog, VHDL, and be proficient with Synopsys DC/FC and Cadence Genus. Travel to other India/global sites is possible as projects demand.

Qualifications

• 2-5 years of experience in Logic Synthesis flows.
• Proficiency in Verilog, System Verilog & VHDL.
• Strong knowledge of RTL2GDSII flow with fundamentals in digital design & implementation.
• Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks
• Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must.
• Experience with advanced technology nodes 7nm and below.
• Hands-on experience in debug & deliver solutions to critical design issues related to synthesis.
• TCL, Perl or Python scripting is a plus.
• Self-motivated team player with a zeal to drive high team performance.
• Good problem solving and debugging skills.

Responsibilities

• Lead a Team of Engineers working on solving the latest design challenges in Logic Synthesis
• Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution
• Work with design community in solving critical design problems to achieve performance, area and power targets
• Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward)
• Develop & deploy training and technical support to customers using Siemens EDA tools

Skills

Verilog

SystemVerilog

VHDL

RTL2GDSII flow

Digital design fundamentals

Problem solving

Tools

Synopsys-DC/FC

Cadence-Genus

Job description

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design.

Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs.

The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime.

This role is based in Bangalore. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come.

This is your role

• Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis
• Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution.
• Work with design community in solving critical designs problems to achieve desired performance, area and power targets.
• Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward).
• Develop & deploy training and technical support to customers using Siemens EDA tools.

We don't need superheroes, just superminds!

• Typically requires minimum of 2-5 years of experience in Logic Synthesis flows
• Proficiency in Verilog, System Verilog & VHDL.
• Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation.
• Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks
• Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must.
• Experience with advance technology nodes 7nm and below.
• Hands-on experience in debug & deliver solutions to critical design issues related to synthesis.
• TCL, Perl or Python scripting is a plus.
• Self-motivated team player with a zeal to drive high team performance.
• Good problem solving and debugging skills.

We are Siemens

A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow!

We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home.

We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.