Senior Post silicon validation

ACL Digital; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

ACL Digital in Bengaluru is seeking an experienced Post-Silicon Debug Engineer to drive silicon enablement and debugging for AMD’s Infinity Fabric across next-gen EPYC, Ryzen, and AI/ML products.

Key duties include validating fabric features and system-level tests, designing debug experiments, and working with firmware/software to define initialization settings and DFD requirements for future microarchitectures.

Qualifications

• 5+ years of experience in post-silicon debug engineering for silicon validation.
• Experience validating Infinity Fabric features, routing configurations and system-level tests.
• Collaborates with firmware/software teams to drive DFD requirements for future microarchitectures.

Responsibilities

• Validate Infinity Fabric features, routing configurations and system-level test requirements.
• Develop debug experiments, triggers, and workarounds to root-cause functional, power and performance anomalies on silicon.
• Collaborate with firmware/software teams to deliver initialization settings and drive DFD requirements for future microarchitectures.

Skills

Computer architecture

Cache coherency

Memory ordering

MMU

SoC power management

Python

C programming

HDLs (Verilog/VHDL)

Oscilloscopes

Logic analyzers

Tools

Oscilloscopes

Logic analyzers

Job description

Experience : 5 years

ACL Digital is looking for an experienced Post-Silicon Debug Engineer (5+ Years) in Bangalore to drive silicon enablement and debug for AMD’s scalable Infinity Fabric interconnect across next-gen EPYC, Ryzen, and AI/ML products.

What You’ll Do:

Partner with architects, DV, and post-silicon teams to validate new Infinity Fabric features, routing configurations, and system-level test requirements.Develop debug experiments, triggers, and workarounds to root-cause functional, power, and performance anomalies on silicon.Collaborate with firmware/software teams to deliver initialization settings and drive Design-for-Debug (DFD) requirements for future microarchitectures.

What We’re Looking For:

Strong expertise in computer architecture, cache coherency, memory ordering, MMU, and SoC power management.Hands-on proficiency with Python/C programming, HDLs (Verilog/VHDL), and lab tools (oscilloscopes, logic analyzers).