Senior Physical Design Engineer / Leads

Eximietas Design; Bengaluru; On-site; INR 15,00,000 - 25,00,000; Full time

Job summary

A technology design company in Bengaluru is seeking a Mid-Senior level Physical Design Engineer with over 10 years of experience in Physical Design using mainstream P&R tools. The role involves working on advanced node designs, developing flows for placement and timing analysis, and providing training to clients. Candidates must have a Bachelor's or Master's in Engineering. Competitive salary and dynamic work environment offered.

Qualifications

• 10+ years of experience in Physical Design.
• Solid experience in place & route flow.
• Experience on Floor Plan design and Static Timing Analysis.

Responsibilities

• Work on 10nm/7nm/5nm designs with customers.
• Develop flow for placement, CTS, routing.
• Provide training and technical support to customers.

Skills

Physical Design expertise

Problem-solving for critical designs

Flow and methodology development

Static Timing Analysis

Physical Verification knowledge

Experience with P&R tools

Education

Bachelor's OR Master's Degree in Engineering (Electronics, Electrical, Telecom, or VLSI)

Job description

Overview

Experience: 10+ Years.

About the job

Qualification Required:

Typically requires a minimum of 10+ years of experience in Physical Design with mainstream P&R tools. Bachelors OR Masters Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering.

Roles And Responsibilities

• Working on 10nm/7nm/5nm or lower nodes designs with various customers for deployment.
• Expertise in solving customers problems for critical designs to achieve desired performance, area, and power targets.
• Responsible for developing flow and methodology for doing placement, CTS, and routing.
• Provide training and technical support to customers.

Required Technical And Professional Expertise

• Solid experience in place & route flow (placement guidelines, clock-tree synthesis, routing, timing optimizations). Experience on hierarchical designs and/or Low Power implementation is an advantage.
• Experience on Synthesis, interfacing with RTL and implementation designers to achieve better quality of results.
• Experience on Floor Plan design, including placement of hard macros, padring, power grid and custom analog routes.
• Experience on Static Timing Analysis related activities (constraints development, parasitic extractions, sign-off requirements).
• Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing).

Interested Candidates please start sharing your resumes: [e-mail]

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Design

Industries

• Engineering Services and Semiconductor Manufacturing

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