Senior Layout Engineer – DPG Layout

Micron Technology; Hyderabad; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Micron Technology, Inc. is seeking an experienced analog/layout engineer to own the development and physical implementation of critical blocks in advanced CMOS nodes.

You will lead layout using AI-assisted workflows, verify with DRC/LVS, and mentor junior engineers while coordinating with Design, CAD, Verification, and Program Management teams. The role emphasizes AI-driven automation for floorplanning, parasitic estimation, and yield optimization, with a focus on delivering high-quality layouts

Qualifications

• 6+ years of analog/custom layout design in advanced CMOS nodes.
• Strong Cadence Virtuoso and Calibre DRC/LVS ownership.
• Experience with memory layouts (DRAM, SRAM, CAM, OTP) and analog blocks.

Responsibilities

• Own layout implementation and physical floorplanning.
• Lead AI-assisted layout workflows and automation.
• Drive on-time delivery with quality and risk mitigation.
• Mentor engineers in analog layout and DFA/DFM practices.

Skills

Analog layout

Layout design

AI-driven automation

Leadership

Mentoring

Verification closure

Education

B.Tech in Electronics, Electronics & Communication, or VLSI Engineering

M.Tech in VLSI Design, Microelectronics, or Electronics Engineering

Tools

Cadence Virtuoso (VLE/VXL)

Calibre DRC/LVS

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Description

Role and Responsibilities

• Own the development and physical implementation of critical analog, mixed‑signal, and custom digital blocks, including block‑level and full‑chip layout ownership.
• Lead layout implementation using AI‑assisted and automated workflows, applying copilot‑based assistants, agentic AI flows, and rule‑aware automation to accelerate placement, routing and optimization.
• Perform and automate layout verification activities, including DRC, LVS, Antenna, Yield, ESD, TOTEM, EM/IR and quality checks.
• Drive on‑time delivery of blocks and partition‑level layouts with predictable quality and risk prediction/mitigation plans.
• Develop and deploy AI‑enabled methodologies for Semi‑automated floorplanning, parasitic estimation, layout consistency checks and best‑practice enforcement, repetitive layout task elimination via SKILL, Python, TCL or agent‑based flows.
• Demonstrate technical leadership in planning, area and cycle‑time estimation, delegation and execution.
• Guide and mentor engineers in Analog layout fundamentals, Automation‑first approach, Design‑for‑quality and design‑for‑yield practices
• Collaborate closely with Design, CAD, Verification, Reliability, and Program Management teams, clearly communicating technical risks, schedule impacts and any optimization opportunities.
• Drive continuous improvement by identifying manual bottlenecks and converting them into scalable automated flows.

Job Requirements

• 6+ years of experience in analog/custom layout design in advanced CMOS technology nodes.
• Strong expertise in Cadence Virtuoso (VLE/VXL) and Calibre DRC/LVS, with hands‑on ownership of verification closure.
• Proven experience in layout of critical analog blocks, including but not limited to Temperature sensors, PLLs, ADCs, DACs, LDOs, bandgaps, reference generators, Charge pumps, etc
• Hands‑on experience with memory layouts, including DRAM, SRAM, CAM, OTP and understanding of array‑to‑periphery integration.
• Deep understanding of analog layout fundamentals, including Matching and symmetry, EM, latch‑up, coupling, crosstalk, IR‑drop, shielding, guard‑ring strategies, parasitic effects.
• Strong ability to interpret design intent and constraints and translate them into high‑quality, manufacturable layouts.
• Proven expertise in defining, developing, and scaling AI‑driven automation and AI‑assisted methodologies for complex layout workflows.
• Demonstrated problem‑solving skills in physical verification, debug, and layout optimization dedicated to improving yield.

Education

• B.Tech in Electronics, Electronics & Communication, or VLSI Engineering
• M.Tech in VLSI Design, Microelectronics, or Electronics Engineering

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high‑performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations, please contact [e-mail]

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

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