Senior ESD Engineer – Technology Development at Micron India

NanoHelp; Hyderabad; On-site; INR 800,000 - 1,500,000; Full time

Benefits offered by this job

Global team collaboration

Cutting-edge tools

Continuous learning opportunities

Innovation fostering culture

Job summary

A semiconductor innovation leader in Hyderabad is seeking a Senior Engineer – TD ESD. The role involves advanced ESD clamp design and addressing circuit verification. Ideal candidates will have a BS/MS/PhD in Electrical Engineering and 3–8 years of relevant experience. The position offers exposure to cutting-edge tools and a global team focused on memory ICs.

Qualifications

• 3–8 years in ESD/LUP circuit design, simulation, or verification.
• Experience with schematic & layout-level ESD analysis.
• Understanding of diffusion/BEOL ESD paths.

Responsibilities

• Advanced ESD clamp design (signal & power).
• Full-chip current density verification using PathFinder & PERC.
• Root-cause and silicon correlation on 1st silicon LUP/ESD failures.

Skills

ESD circuit design

Silicon correlation

Nanoscale circuit behavior

Data-driven mindset

Passion for innovation

Education

BS/MS/PhD in Electrical Engineering

Tools

Cadence

PERC

PathFinder

Job description

Micron Technology is hiring a Senior Engineer – TD ESD for its Hyderabad site. This role is ideal for specialists in nanodevice reliability, semiconductor protection design, and ESD/Latch-Up modeling. Contribute to robust, scalable memory design with industry-leading tools.

Job Details

Field: Nanotechnology, Electrical Engineering, Microelectronics, Reliability Engineering, Applied Physics

Title: Senior Engineer – TD ESD

Organization: Micron Technology Inc.

Work Location: Hyderabad, Telangana, India

Research Focus: ESD/Latch-Up Design, ESD Clamp Simulation, High-Current Reliability

Responsibilities

In this hands-on engineering position, you’ll work at the intersection of nanoelectronic reliability and memory system integrity. Micron’s TD ESD team is at the forefront of ESD clamp innovation, simulating and validating critical protection paths for NAND, DRAM, and emerging memory platforms.

• Advanced ESD clamp design (signal & power)
• TLP and vf-TLP based circuit characterization
• Full-chip current density verification using PathFinder & PERC
• Development of ESD/LUP design rules from nanoscale circuit behavior
• Root-cause and silicon correlation on 1st silicon LUP/ESD failures

Requirements

Required Education: BS/MS/PhD in Electrical Engineering, Microelectronics or related field

Required Experience: 3–8 years in ESD/LUP circuit design, simulation, or verification

• Experience with Cadence, PERC, or PathFinder for schematic & layout-level ESD analysis
• Understanding of diffusion/BEOL ESD paths, including nanoscale resistance modeling
• Data-driven mindset, especially for silicon correlation and DOE validation
• Passion for innovation and building scalable solutions in memory ICs

Preferred: 5+ years in high-speed/ESD design, Knowledge of nanostructured ESD clamps, poly-M1 interaction, or 3D memory

What We Offer

Micron’s Hyderabad site is a rising center for semiconductor innovation, driving the next generation of DRAM, NAND, and novel memory architectures. You’ll benefit from:

• A global team of device physicists, ESD technologists, and circuit designers
• Cutting-edge tools and AI/ML-powered design validation
• Exposure to both R&D and production-level platforms
• A culture of patent generation, continuous learning, and innovation