Senior Engineer – RV (EM/IR)

TylSemi, Inc.; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

TylSemi, Inc. is seeking a Senior Engineer – EM/IR in Bengaluru. In this role, you'll perform power integrity analysis for advanced-node SoC designs, collaborating with various teams to ensure reliable power delivery and signoff closure.

The ideal candidate has over 5 years of EM/IR analysis experience and a strong understanding of static and dynamic IR drop analysis. The position supports a hybrid work model, favoring candidates with a proactive, ownership mindset.

Qualifications

• 5+ years of experience in EM/IR analysis or Physical Design signoff roles.
• Strong understanding of IR drop analysis and electromigration concepts.
• Hands-on experience with industry-standard tools.

Responsibilities

• Perform IR drop and electromigration analysis for advanced-node designs.
• Collaborate with Physical Design and Package teams to optimize power delivery networks.
• Develop and improve automation flows and signoff methodologies.

Skills

EM/IR analysis

Power integrity analysis

Physical Design signoff

Scripting (Tcl, Perl, Python)

Education

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline

Tools

Cadence Voltus

Ansys RedHawk

Job description

About this position

About TylSemi, Inc. The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TylSemi builds the chiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The semiconductor industry is going through its biggest architectural shift in 40 years: Moore's Law is dead, Custom silicon is now mainstream, IO and power are the bottleneck. We are entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No politics, no bureaucracy. There are no layers, no approval chains, no corporate theater.

Remote-Friendly, Global Team

US team: Bay Area preferred, but we hire the best people regardless of location

India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

Role Overview

We are looking for a highly motivated Senior Engineer – EM/IR to join the Physical Design and Signoff team. In this role, you will be responsible for performing power integrity analysis including IR drop and electromigration (EM) checks for advanced‑node SoC designs. You will work closely with Physical Design, Power, and Package teams to ensure robust power delivery network implementation and reliable signoff closure. The ideal candidate should have strong fundamentals in power integrity analysis, signoff methodologies, and advanced‑node implementation challenges.

What You’ll Do

• Perform block‑level and full‑chip IR drop and electromigration (EM) analysis for advanced‑node designs.
• Analyze and debug static and dynamic IR violations to achieve power integrity signoff closure.
• Collaborate with Physical Design, Floorplanning, CTS, Routing, and Package teams to optimize power delivery networks.
• Run and interpret power integrity analysis across multiple operating conditions and scenarios.
• Support EM analysis by evaluating current density, reliability limits, and thermal impacts.
• Develop and improve IR/EM automation flows, scripts, and signoff methodologies.
• Support tape‑out activities and ensure clean IR/EM signoff delivery.

What We’re Looking For

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI‑related discipline.
• 5+ years of experience in EM/IR analysis, power integrity, or Physical Design signoff roles.
• Strong understanding of static and dynamic IR drop analysis, electromigration concepts, and power grid optimization.
• Hands‑on experience with industry‑standard tools such as Cadence Voltus, Ansys RedHawk, or equivalent.
• Good understanding of Physical Design flow including floorplanning, placement, CTS, routing, and extraction.
• Proficiency in Tcl, Perl, Python, or Shell scripting for automation and flow enhancement.

Good to Have

• Experience with advanced technology nodes such as 7nm, 5nm, or below.
• Exposure to package‑aware analysis, thermal analysis, and low‑power methodologies.
• Understanding of power‑aware signoff methodologies and reliability verification flows.

Success in This Role Looks Like

• Achieving clean IR/EM signoff with robust power integrity across all operating conditions.
• Efficient identification and resolution of power integrity and reliability issues.
• Improved productivity through automation and methodology enhancements.
• Successful collaboration across cross‑functional teams leading to timely tape‑out execution.

Location

Hybrid / On‑site – Bengaluru/ Remote - India