Senior Engineer, Physical Design

Synopsys Inc; Bengaluru; On-site; INR 900,000 - 1,400,000; Full time

Job summary

Synopsys Inc in Bengaluru, India seeks a Senior Engineer in Physical Design focused on PnR implementation and flow methodologies. You will drive PnR for complex designs using Fusion Compiler or Cadence Innovus and contribute to signoff with ICV, RedHawk, PrimeTime, and StarRC.

The role emphasizes improving PPA, debugging flows, and collaborating with cross‑functional teams worldwide. A BS/B.Tech in EE or ECE with 3+ years of PnR experience is required; MS/M.Tech with 2+ years is also acceptable.

Qualifications

• BS/B.Tech in EE or ECE with 3+ years of relevant experience, or MS/M.Tech with 2+ years.
• Strong hands-on experience in PnR design implementation and flow methodologies.
• Familiarity with Fusion Compiler (FC) or Innovus and signoff tools.
• Experience driving PPA improvements and optimization activities.

Responsibilities

• Drive Place and Route (PnR) implementation for complex designs.
• Execute and optimize physical design flows across lifecycle stages.
• Work with Fusion Compiler and/or Innovus for design implementation.
• Perform physical design signoff using ICV, RedHawk, PrimeTime, StarRC.
• Analyze results and identify opportunities for PPA improvement.
• Contribute to continuous improvement of flows and methodologies.
• Debug complex implementation and flow issues with strong analysis.
• Collaborate with global engineering teams across geographies.

Skills

PnR design implementation

Flow methodologies

FC or Innovus

PPA optimization

Debugging

Cross-functional collaboration

Education

BS/B.Tech in EE or ECE

MS/M.Tech in EE/ECE

Tools

Fusion Compiler

Cadence Innovus

IC Validator

RedHawk

PrimeTime

StarRC

Job description

Senior Engineer, Physical Design – PnR Implementation & Methodology

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are an experienced Physical Design engineer with strong expertise in Place and Route (PnR) design implementation and flow methodologies. You have a comprehensive understanding of the complete PnR development flow and hands-on experience using industry-standard physical design tools such as Synopsys Fusion Compiler (FC) or Cadence Innovus.

You understand physical design signoff methodologies and have exposure to tools such as IC Validator (ICV), RedHawk, PrimeTime, and StarRC, or equivalent solutions. Along with executing designs, you are interested in continuously improving implementation flows, methodologies, and Power, Performance, and Area (PPA).

You bring strong debugging, analytical, and problem-solving capabilities and are comfortable collaborating with cross-cultural, geographically distributed, and matrixed engineering teams.

What You’ll Be Doing

• Drive Place and Route (PnR) implementation for complex semiconductor designs.
• Execute and optimize physical design flows across key stages of the PnR lifecycle.
• Work extensively with Fusion Compiler (FC) and/or Innovus for design implementation.
• Perform and support physical design signoff using methodologies and tools such as ICV, RedHawk, PrimeTime, and StarRC, or similar.
• Analyze implementation results and identify opportunities for PPA improvement.
• Contribute to continuous improvement of physical design flows, methodologies, and flow usage.
• Debug complex implementation and flow issues using strong analytical and problem-solving skills.
• Collaborate with engineering teams across different functions, geographies, and cultures.
• Explore productivity improvements through modern engineering and AI-assisted tools such as Cursor.

The Impact You Will Have

• Help deliver high-quality physical design implementation for advanced semiconductor designs.
• Improve Power, Performance, and Area (PPA) through design and flow optimization.
• Enhance the efficiency, robustness, and scalability of PnR implementation methodologies.
• Identify and resolve complex physical design and signoff issues.
• Contribute to continuous improvement and automation of implementation flows.
• Enable effective collaboration across global and cross-functional engineering teams.

What You’ll Need

• BS/B.Tech in Electrical Engineering (EE), Electronics & Communication Engineering (ECE), or equivalent with 3+ years of relevant experience, OR
• MS/M.Tech in EE, ECE, or equivalent with 2+ years of relevant experience.
• Strong hands‑on experience in PnR design implementation and/or PnR flow methodologies.
• Comprehensive understanding of the PnR development flow.
• Good hands‑on experience with Fusion Compiler (FC) or Innovus.
• Good understanding of physical design signoff tools and methodologies.
• Experience or exposure to ICV, RedHawk, PrimeTime, StarRC, or similar tools.
• Experience contributing to PPA improvement and flow optimization activities.
• Strong debugging, analytical, and problem‑solving skills.
• Excellent collaboration and influencing skills with the ability to work effectively in cross‑cultural, multi‑geography, and matrixed teams.
• Exposure to AI‑assisted engineering tools such as Cursor is a plus.

Who You Are

• You approach complex physical design challenges methodically and drive them through resolution.
• You enjoy debugging implementation, timing, physical verification, and flow‑related issues.
• You look beyond basic design closure and continuously seek opportunities to improve PPA and implementation efficiency.
• You communicate technical issues clearly and collaborate effectively with geographically distributed teams.
• You are comfortable taking ownership while working as part of a broader engineering organization.
• You are curious about new methodologies, automation, and AI‑assisted engineering approaches.

The Team You'll Be Part Of

You will be part of a physical design engineering team focused on PnR implementation, design closure, signoff, flow methodology, and PPA optimization. You will collaborate with cross‑functional and geographically distributed engineering teams to improve implementation quality, resolve complex design challenges, and continuously enhance physical design methodologies.

Rewards and Benefits

• We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
• Our total rewards include both monetary and non‑monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.